Clock Data Recovery Phase Detection Without Garbage Pulses
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Solution Overview
Problem
High-speed serial communication methods face challenges in generating reliable recovery data due to difficulties in synchronizing clock and data signals, leading to inefficient data transfer rates in clock data recovery circuits.
Innovation Solution
A clock data recovery circuit is designed with a phase detector that uses sampling latch and edge detection circuits to generate a recovery clock signal from an embedded clock signal, and a data recovery circuit that uses this clock to produce reliable data, preventing garbage pulses and adjusting pulse widths for accurate phase tracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the data transfer rate is increased in serial communication, then communication speed is improved, but the clock data recovery circuit cannot generate reliable recovery data
Solution Approach 1:
The phase detector performs preliminary sampling of the input data signal at multiple phases before the actual data recovery operation. By pre-detecting the phase of the embedded clock signal through sampling at different phases (0°, 90°, 180°, 270°), the system prepares the phase information in advance, allowing the recovery clock to be accurately synchronized even at high data transfer rates.
Solution Approach 2:
The edge detection circuit provides feedback by comparing the sampled signals from different phases and generating phase control signals that adjust the recovery clock phase. This feedback mechanism continuously monitors the phase alignment between the recovery clock and the embedded clock, making real-time corrections to maintain reliable data recovery at high speeds.
2Device complexity
If conventional phase detection methods are used, then circuit simplicity is maintained, but garbage pulses are generated and phase tracking accuracy deteriorates
Solution Approach 1:
The phase detection function is segmented into multiple independent sampling operations at different phases (0°, 90°, 180°, 270°) rather than using a single conventional phase detector. Each sampling latch captures the input data signal at a specific phase, and the edge detection circuit processes these segmented samples to generate accurate phase control signals without producing garbage pulses.
Solution Approach 2:
The sampling latch circuit acts as an intermediary between the input data signal and the edge detection circuit. It buffers and phases the sampled signals, providing clean, synchronized inputs to the edge detection circuit. This intermediary structure prevents garbage pulse generation while maintaining accurate phase information for tracking.
3Speed
If the phase detector operates continuously, then phase tracking responsiveness is improved, but power consumption increases
Solution Approach 1:
The phase detector operates periodically by sampling the input data signal at discrete phase intervals (0°, 90°, 180°, 270°) rather than continuously. The sampling latch circuits are activated at specific phases of the reference clock, and the edge detection circuit processes these periodic samples to generate phase control signals. This periodic operation maintains responsive phase tracking while significantly reducing power consumption compared to continuous operation.
Data Source
AI summary
A clock data recovery circuit configured to receive an input data signal that includes an embedded clock signal includes a clock recovery circuit including a phase detector configured to detect a phase of the embedded clock signal and to generate a recovery clock signal from the input data signal based on the detected phase; and a data recovery circuit configured to generate a recovery data signal from the input data signal by using the recovery clock signal. The phase detector includes a sampling latch circuit configured to output a first sample signal and a second sample signal from the input data signal; and an edge detection circuit configured to generate a phase control signal based on the first sample signal and the second sample signal and output the phase control signal in a period in which the second sample signal is output from the sampling latch circuit.