Clock Recovery Circuit Using Phase Interpolation to Reduce Jitter
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Solution Overview
Problem
Conventional clock recovery circuits face challenges with high power dissipation, large chip area, design complexity, and noise, particularly in maintaining jitter characteristics and increasing data transmission speed.
Innovation Solution
A recovery circuit and method that include a phase detector, quadrant decision unit, quadrant controller, charge pump unit, and phase interpolator, allowing for continuous maintenance of initial voltage control signals and selection of clocks with 90-degree phase delays, controlled by a single charge pump circuit to reduce jitter and enhance data transmission speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase locked loop (PLL) is used for clock recovery, then clock data synchronized to higher-rate serial input data can be provided, but power dissipation increases and chip area enlarges
Solution Approach 1:
The patent extracts the essential function of phase detection and control from the complete PLL system. By using a phase detector to generate up/down signals and a charge pump circuit to convert these signals into voltage adjustments, the system achieves clock recovery without implementing the full PLL architecture, thereby reducing power dissipation while maintaining synchronization capability
Solution Approach 2:
The patent uses a reference clock signal as a template to generate the recovered clock. By comparing the phase of the reference clock with the serial input data and adjusting the reference clock's phase through charge pump control, the system creates a copied version of the clock that is synchronized to the high-speed data stream without requiring the entire PLL mechanism
2Reliability
If a phase locked loop (PLL) is used for clock recovery, then clock data synchronized to higher-rate serial input data can be provided, but chip area enlarges
Solution Approach 1:
The patent removes unnecessary components from the traditional PLL architecture, retaining only the essential phase detector and charge pump circuit. This extraction of core functionality eliminates redundant circuitry, significantly reducing chip area while preserving the clock synchronization capability required for high-speed serial data recovery
Solution Approach 2:
The patent combines the phase detection and charge pump functions into a tightly integrated circuit block. By merging these functions and sharing common circuit elements, the design achieves efficient space utilization on the chip, reducing the overall area required compared to a conventional PLL implementation
3Reliability
If conventional clock recovery circuits are used, then clock synchronization can be achieved, but jitter characteristics deteriorate
Solution Approach 1:
The patent implements a feedback mechanism where the phase detector continuously compares the reference clock phase with the serial input data phase. The resulting up/down signals are fed back to the charge pump circuit, which adjusts the reference clock voltage to minimize phase difference. This closed-loop feedback ensures accurate clock synchronization while minimizing jitter by continuously correcting phase deviations
Solution Approach 2:
The patent employs dynamic voltage control of the reference clock through the charge pump circuit. By dynamically adjusting the clock voltage based on real-time phase detection results, the system can adapt to varying signal conditions and maintain optimal jitter performance. The dynamic nature of the charge pump allows rapid response to phase variations, improving jitter characteristics compared to static conventional circuits
4Reliability
If conventional clock recovery circuits are used, then clock synchronization can be achieved, but data transmission speed increases difficulty
Solution Approach 1:
The patent segments the clock recovery function into distinct modular components: a phase detector that generates up/down signals and a charge pump circuit that converts these signals to voltage control. This segmentation allows independent optimization of each module and simplifies the overall design process, making it easier to achieve reliable clock synchronization at high data transmission speeds compared to monolithic conventional approaches
Data Source
AI summary
A recovery circuit may include a phase detector, a quadrant decision unit, a quadrant controller, a charge pump unit, and a phase interpolator. The phase detector may compare a phase of input data with a phase of a current output clock to generate first up signal and first down signal and the quadrant decision unit may determine the phase location for the current output clock and output quadrant decision signals based on a phase location. The quadrant controller may output a second up signal and a second down signal based on the first up signal and the first down signal and the quadrant decision signals, and the charge pump unit may output a first and second phase control voltage based on the second up signal and the second down signal. The phase interpolator may select clocks from a plurality of clocks based on the quadrant decision signals and output an output clock signal based on the selected clocks.