Data Phase Adjustment in Clock Recovery to Cut Bang-Bang Jitter
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Solution Overview
Problem
Existing clock and data recovery devices suffer from increased jitter in bang-bang loops due to significant loop delay, which affects the timing margin and recovery characteristics of internal clocks and data.
Innovation Solution
The proposed clock and data recovery device incorporates a data phase adjuster with capacitors and switches to immediately reflect up and down signals from the phase detector to the input timing, reducing loop delay and synchronizing clock and data phases effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional charge pump and loop filter are used to control the voltage controlled oscillator, then the clock frequency can be adjusted, but significant loop delay occurs which increases jitter
Solution Approach 1:
The patent extracts the phase adjustment function from the traditional charge pump loop filter path and implements it directly at the data input timing. By removing the intermediate charge pump and loop filter components from the phase adjustment path, the loop delay is significantly reduced while maintaining the ability to adjust clock frequency and phase based on phase detector signals
Solution Approach 2:
The patent introduces a new intermediary component (phase adjustment circuit directly coupled to data input timing) that mediates between the phase detector output and the data sampling timing. This intermediary directly adjusts the data input timing based on up/down signals without requiring the traditional charge pump and loop filter, thereby reducing loop delay while maintaining control functionality
2Reliability
If the loop delay is reduced by direct phase adjustment, then jitter is reduced, but the device complexity increases due to additional phase adjustment components
Solution Approach 1:
The patent merges the phase adjustment functionality directly into the data input timing path by coupling the phase detector output directly to the data sampling timing control. This integration eliminates the need for separate charge pump and loop filter components, reducing device complexity while achieving direct phase adjustment and jitter reduction
3Reliability
If traditional feedback control is used, then frequency stability can be maintained, but tracking performance degrades due to delayed response
Solution Approach 1:
The patent implements preliminary action by directly adjusting the data input timing based on phase detector signals before the traditional feedback loop would process them. The phase adjustment occurs in advance of the sampling event, allowing the system to respond immediately to phase errors and track timing changes with superior speed while maintaining frequency stability through the direct coupling mechanism
Data Source
AI summary
A clock and data recovery device includes an equalizer that compensates for channel loss of input data, a phase detector that compares a data output from the equalizer with a clock fed back and outputs an up signal and a down signal, a charge pump that operates according to the up signal and the down signal and outputs a control signal, a loop filter that removes high-frequency components included in the control signal, a voltage controlled oscillator that changes a frequency of the clock and outputs a clock with changed frequency, and a data phase adjuster that synchronizes the clock output from the voltage controlled oscillator and the data output from the equalizer by adjusting a phase of the data output from the equalizer by receiving the up signal and the down signal output from the phase detector.