Clock Data Recovery Circuit With Simplified Phase-Frequency Locking
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Solution Overview
Problem
Existing clock data recovery circuits have complex structures due to the need for high-order filters in phase locking loops and the interaction between phase and frequency locking loops, which complicates stability considerations.
Innovation Solution
A clock data recovery circuit and method that utilize a time delay loop for phase alignment, a frequency locking loop to adjust the clock signal frequency, and a deserializer to deserialize the input data, avoiding the introduction of a phase integral factor and simplifying the circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase locking loop with high-order filter is used to ensure system stability, then the stability of the system is improved, but the device complexity increases
Solution Approach 1:
The patent extracts and eliminates the phase integral factor from the phase locking loop system. By removing this component that causes phase accumulation and requires high-order filters for compensation, the system achieves stability without the complexity of high-order filter circuits. The charge pump output directly controls the VCO without integrating phase errors through a capacitor.
Solution Approach 2:
The patent changes the control parameter relationship by making the VCO frequency directly proportional to the charge pump output current, rather than requiring integration of the charge pump output through a capacitor. This parameter change eliminates the need for phase accumulation and the associated high-order filter complexity while maintaining system stability.
2Reliability
If a frequency locking loop is added to work cooperatively with the phase locking loop, then the frequency locking capability is improved, but the device complexity increases
Solution Approach 1:
The patent merges the frequency locking function into the existing phase locking loop by using the same charge pump and VCO components. The frequency locking is achieved by controlling the VCO frequency through the charge pump output without requiring a separate frequency locking loop, thereby reducing circuit complexity while maintaining frequency locking capability.
3Reliability
If phase accumulation is performed constantly during phase locking, then the phase locking function is improved, but the device complexity increases due to the need for high-order filters
Solution Approach 1:
The patent removes the phase accumulation mechanism (capacitor integration in the loop filter) from the system. Instead of constantly integrating phase errors through a capacitor that requires high-order filters for compensation, the system uses direct proportional control where the charge pump output current directly adjusts the VCO frequency to match the input signal frequency.
Data Source
AI summary
A clock data recovery circuit and a clock data recovery method are provided. The clock data recovery circuit includes a time delay loop (100), a frequency locking loop (200) and a deserializer (300). The time delay loop (100) is configured to delay input data according to a phase of a clock signal to realize phase alignment; the frequency locking loop (200) is connected to the time delay loop (100), and is configured to adjust a frequency of the clock signal according to the delayed input data to make the frequency of the clock signal be consistent with a frequency of the input data; and the deserializer (300) is respectively connected to the time delay loop (100) and the frequency locking loop (200), and is configured to deserialize the input data according to the clock signal.