Three-Path Clock Recovery for Phase Interpolator Nonlinearity
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Solution Overview
Problem
High-speed digital communications face challenges in clock recovery due to increased sensitivity to nonlinearities in phase interpolators, particularly at tens-of-gigahertz symbol rates, where silicon-based CMOS circuit implementations fail to provide adequate performance.
Innovation Solution
A digital communications receiver incorporating a fractional-N phase lock loop with multiple feedback paths to minimize timing and frequency errors, using a phase interpolator, timing error estimator, and frequency error accumulators to produce a clock signal that reduces sensitivity to nonlinearities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a phase interpolator is used to generate sampling signals at tens-of-gigahertz rates, then the symbol rate and communication speed increase, but the sensitivity to nonlinearities in the phase interpolator increases, causing degraded clock recovery performance
Solution Approach 1:
The patent implements a feedback mechanism where timing error information from the sampling process is fed back to adjust and correct the phase interpolator's output. This closed-loop feedback compensates for the nonlinearities that occur at high symbol rates, maintaining clock recovery performance while enabling higher communication speeds.
2Ease of manufacture
If existing clock recovery solutions are implemented in silicon-based CMOS circuits, then the device can be manufactured with standard processes, but the circuits approach device design limits and fail to provide adequate performance at high symbol rates
Solution Approach 1:
The patent modifies operational parameters within the CMOS circuit, specifically implementing a feedback-based timing error correction mechanism that changes how the phase interpolator operates. This allows the standard silicon-based CMOS implementation to achieve adequate performance at high symbol rates by dynamically adjusting parameters based on timing error feedback.
3Productivity
If the symbol rate is increased to improve data transmission capacity, then the communication throughput increases, but intersymbol interference and timing error sensitivity increase, making it difficult to determine transmitted symbols
Solution Approach 1:
The patent uses feedback of timing error information to continuously correct and refine the sampling clock timing. This feedback mechanism compensates for the increased timing sensitivity and intersymbol interference that occur at higher symbol rates, maintaining symbol detection accuracy while enabling higher data transmission capacity.
Data Source
AI summary
An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop that provides a clock signal; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal; a timing error estimator that produces a timing error signal; a first feedback path coupling the timing error signal to the phase interpolator to minimize a phase component of the estimated timing error; a second feedback path coupling the timing error signal to the phase interpolator; and a third feedback path coupling the timing error signal to the fractional-N phase lock loop, the second and third feedback paths minimizing a frequency offset component of the estimated timing error.