Clock Recovery Phase Rotation for Fast Burst-Mode Lock

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Solution Overview

Problem

Burst-mode communication systems, particularly in chip-to-chip communications, face challenges in reducing clock and data recovery lock time to within tens of bit times, which is crucial for efficient power management.

Innovation Solution

A PLL-based clock and data recovery apparatus that includes a sampler, phase detector, phase rotator, control unit, and loop filter, which samples input data signals at transition edges, determines phase differences, and dynamically adjusts clock signals to quickly align data transitions with sampling edges, reducing lock-in time and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional clock and data recovery methods are used, then system reliability is maintained, but lock time becomes too long for burst-mode operations

Engineering Contradiction:
Improvelock timeVSAvoidphase detection accuracy
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent implements a dual-mode phase detection mechanism that dynamically switches between coarse phase detection (for rapid initial alignment) and fine phase detection (for precise final locking). The system transitions from a first phase detector operating in coarse mode to a second phase detector operating in fine mode, enabling the lock time to be reduced while maintaining reliability through adaptive operation modes.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The phase detection process is segmented into two distinct stages: coarse phase detection and fine phase detection. Each stage uses a specialized phase detector optimized for its specific function, allowing the system to rapidly acquire initial phase alignment and then precisely refine the lock, thereby reducing overall lock time without sacrificing final accuracy.

Inventive Principle:
Principle #1Segmentation

2Use of energy by moving object

If the link is turned on and off frequently for burst-mode communication, then power consumption is reduced, but lock time must be minimized to maintain efficiency

Engineering Contradiction:
Improvepower consumptionVSAvoidlock time
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The system performs preliminary coarse phase detection to quickly establish initial phase alignment before transitioning to fine phase detection. This preliminary action significantly reduces the time required to achieve lock when the link is turned on, making frequent burst-mode operations more efficient without excessive power consumption.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If a single phase detector is used, then device complexity is reduced, but the ability to achieve both fast acquisition and precise tracking is compromised

Engineering Contradiction:
Improvephase alignment speedVSAvoidphase detector configuration
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system dynamically switches between two phase detectors with different characteristics, using the first detector for rapid coarse acquisition and the second detector for precise fine tracking. This dynamic adaptation allows the system to achieve both fast phase alignment speed and high precision without requiring a single overly complex detector design.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Each phase detector is designed with a specific function: the first detector handles coarse phase detection for rapid acquisition, while the second detector handles fine phase detection for precise tracking. This multi-functional architecture allows the system to perform both fast alignment and precise tracking, with each detector optimized for its specific role.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9590640B1Clock and data recovery apparatus and method of the same
Publication Date: 2017.03.07 REALTEK SEMICON CORP
  • US9590640B1 patent drawing
  • US9590640B1 patent drawing
  • US9590640B1 patent drawing

AI summary

An electronic apparatus including an oscillator, a sampler, a phase detector, a phase rotator and a loop filter is provided. The oscillator generates a reference and an auxiliary clock signal offset by 90 degrees. The sampler samples an input data signal at each transition edges to generate primary sampled signals. The phase detector determines a phase difference of a data transition of the input data signal relative to a data-sampling edge. The phase rotator rotates the primary sampled signals and the reference clock signal according to the phase difference. The loop filter generates a control voltage to control the oscillator to vary phases of the reference clock signal and the auxiliary clock signal according to phase difference of the data transition relative to the rotated reference clock signal.