Clock Recovery Phase Rotation for Fast Burst-Mode Locking
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Solution Overview
Problem
Burst-mode communication systems face challenges in reducing clock and data recovery lock time to within tens of bit times, particularly in chip-to-chip communications, where quick link activation and deactivation are necessary to conserve power.
Innovation Solution
A PLL-based clock and data recovery apparatus that includes a sampler, phase detector, phase rotator, control unit, and loop filter, which samples input data signals at transition edges, determines phase differences, and dynamically adjusts clock signals to align data transitions with reference clocks, reducing lock-in time and power consumption through phase rotation and bandwidth control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional clock and data recovery methods are used, then the system can maintain stable operation, but the lock time becomes too long to meet burst-mode communication requirements
Solution Approach 1:
The patent applies preliminary action by performing coarse phase adjustment before fine phase adjustment. The coarse phase detector first brings the clock signal into rough alignment with the data signal, establishing a preliminary locked state. This preliminary action reduces the initial phase difference significantly, allowing the subsequent fine phase detector to achieve precise locking much faster than conventional methods that attempt fine adjustment from a large initial phase difference.
Solution Approach 2:
The patent segments the phase detection and adjustment process into two distinct stages: coarse phase detection and fine phase detection. The coarse phase detector handles large phase deviations using a wider detection range, while the fine phase detector handles small phase deviations with higher precision. This segmentation allows each detector to be optimized for its specific function, achieving both fast initial acquisition and precise final locking.
2Productivity
If the lock time is reduced to tens of bit times, then burst-mode power saving is achieved, but the phase detection accuracy deteriorates
Solution Approach 1:
The patent divides phase detection into coarse and fine stages, where the coarse phase detector uses a wider detection range to quickly reduce large phase errors, and the fine phase detector uses a narrower, more precise detection range to accurately eliminate residual phase errors. This segmentation enables fast initial acquisition without sacrificing final phase detection accuracy.
Solution Approach 2:
The patent applies local quality by using different detection characteristics in different phases of the locking process. The coarse phase detector is designed with broader detection capabilities for initial acquisition, while the fine phase detector is optimized with higher precision for final adjustment. Each detector's characteristics are locally optimized for its specific function in the locking sequence.
3Speed
If a wide phase detection range is used to handle large phase differences, then the initial locking speed improves, but the precision for small phase adjustments deteriorates
Solution Approach 1:
The patent segments the phase detection function into two specialized detectors: a coarse phase detector with wide detection range for fast initial locking, and a fine phase detector with narrow high-precision range for accurate final adjustment. This segmentation resolves the contradiction by assigning different detection ranges to different stages of the locking process.
Solution Approach 2:
The patent implements dynamic switching between coarse and fine phase detection modes. The system automatically transitions from coarse detection when large phase differences exist to fine detection when the phase difference becomes small. This dynamic adaptation allows the system to maintain optimal detection characteristics throughout the entire locking process, achieving both fast initial acquisition and precise final locking.
Data Source
AI summary
An electronic apparatus including a PLL unit to an original clock signal, a pair of phase interpolators, a sampler, a phase detector, a control unit and a loop filter is provided. The phase interpolators receive the original clock signal and generate a reference clock signal and an auxiliary clock signal offset by 90 degrees having transition edges. The sampler samples an input data signal at each of the transition edge. The phase detector determines a phase difference of a data transition of the input data signal relative to the reference clock signal. The control unit superimposes an adjusting phase on phases of the reference clock signal and the auxiliary clock signal according to the phase difference. The phase detector determines that the phase difference is within a predetermined range. The loop filter superimposes a varying phase on the phases of the reference clock signal and the auxiliary clock signal accordly.