Clock-Data Recovery Circuit for Fast Re-Locking After Phase Steps
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Solution Overview
Problem
Conventional clock-data recovery (CDR) systems face significant delays in re-locking the clock signal when large phase changes occur in the incoming data stream, such as between 90 and 180 degrees, which can lead to synchronization issues in high-speed serial data transmission.
Innovation Solution
The system incorporates phase alignment circuitry, clock generator circuitry, and time-to-digital converter circuitry to generate a plurality of base phase clock signals, allowing for rapid adjustment to large phase changes by selecting the closest aligned clock signal and using it to re-time the data signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL circuitry is used to maintain clock signal alignment, then the system operates reliably under small phase changes, but the re-locking time becomes unacceptably long when large phase changes occur between 90 and 180 degrees
Solution Approach 1:
The phase alignment circuitry generates multiple feedback clock signals (e.g., four signals) separated by equal phase intervals (e.g., 90 degrees). This segmentation of the clock signal generation allows the system to cover a full 360-degree phase range with discrete clock options, enabling rapid selection of the appropriate clock signal without gradual adjustment, thus solving the long re-locking time problem while maintaining reliable alignment.
2Speed
If multiple clock signals are generated to cover large phase changes, then the re-locking speed improves, but the device complexity increases due to additional circuitry
Solution Approach 1:
The system dynamically selects which feedback clock signal to use based on the detected phase relationship between the incoming data stream and the output clock signal. The phase detector continuously monitors phase differences and controls the multiplexer to switch between different feedback clock signals as needed. This dynamic adaptation allows rapid response to large phase changes without permanently maintaining complex circuitry for all possible phase conditions simultaneously.
Solution Approach 2:
The phase alignment circuitry pre-generates multiple feedback clock signals with predetermined phase separations before phase detection is needed. By having these clock signals ready in advance at different phase offsets, the system can immediately select the appropriate clock signal when a large phase change is detected, eliminating the need for gradual phase adjustment and achieving fast re-locking without complex real-time generation circuitry.
Data Source
AI summary
A clock-data recovery system and method promotes fast adjustment to large phase changes in the incoming data signal. The system can include phase alignment circuitry, clock generator circuitry, time-to-digital converter circuitry, and sampling circuitry. The phase alignment circuitry uses the incoming data signal and a feedback clock signal to generate an output clock signal. The clock generator circuitry uses the output clock signal to generate base phase clock signals of different phases or polarities. The time-to-digital converter circuitry uses the base phase clock signals and the incoming data signal to generate the feedback clock signal. The time-to-digital converter circuitry bases the feedback clock signal on the base phase clock signal that is aligned more closely in phase with the incoming data signal than the other base phase clock signals. The sampling circuitry re-times or recovers the data signal using one or more of the base phase clock signals.