Clock Recovery Phase Switching for Fast Lock and Zero Phase Error
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Solution Overview
Problem
Prior art clock recovery devices in packet networks, such as those using the Precision Time Protocol (PTP), face challenges in achieving zero steady state frequency and phase error, especially in boundary clocks, and fail to maintain low closed loop gain peaking during mode and reference switching.
Innovation Solution
A clock recovery device with a modified phase/frequency locked loop system, featuring a transient non-linear phase-adjust system for initial fast phase alignment and a secondary phase path for steady-state correction, utilizing pure offset information from synchronization packets to adjust the control input of a controlled oscillator, and activating/de-activating a transient phase adjuster to manage transit delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a non-linear phase adjustment block is used for fast phase locking, then phase alignment speed is improved, but residual phase error increases during mode and reference switching
Solution Approach 1:
The phase adjustment function is divided into two separate blocks: a non-linear phase adjustment block for fast initial phase locking, and a secondary phase adjustment path for steady-state precision correction. This segmentation allows each block to specialize in one aspect of phase adjustment, resolving the contradiction between speed and precision.
Solution Approach 2:
The system dynamically switches between the transient phase adjuster and secondary phase path based on operating conditions. The transient phase adjuster is activated during mode and reference switching for fast re-locking, then deactivated when the secondary phase path takes over for precision maintenance, creating a dynamic adaptation to different operational states.
2Device complexity
If the same input phase sample is used for both frequency and phase paths, then device complexity is reduced, but the ability to reduce residual phase error deteriorates
Solution Approach 1:
The single phase sample input is segmented into two independent processing paths: one path processes the original phase sample for frequency adjustment, while the other path processes a corrected phase sample for precise phase adjustment. This segmentation enables both paths to optimize their respective functions without interfering with each other.
Solution Approach 2:
A phase correction value is introduced as an intermediary element that mediates between the original phase sample and the secondary phase path. This intermediary allows the system to preserve the original phase information for frequency control while providing corrected phase information for precision phase control, eliminating the need to choose between the two.
3Speed
If a transient phase adjuster is continuously active, then phase alignment speed is maintained, but closed loop gain peaking increases above 0.1 dB
Solution Approach 1:
The transient phase adjuster operates periodically rather than continuously - it is activated only during transient conditions such as mode switching or reference changes, then deactivated when steady-state conditions are reached. This periodic activation maintains fast phase alignment capability when needed while preserving closed-loop stability during normal operation.
Solution Approach 2:
The system dynamically adjusts the gain characteristics by switching between two operational modes: a high-gain transient mode for fast phase locking and a low-gain steady-state mode for stable operation. This dynamic gain adjustment resolves the contradiction between maintaining fast response and preserving stability margins.
Data Source
AI summary
A clock recovery device recovers a master clock over a packet network from incoming synchronization packets. A frequency locked loop generates a control input to a controlled oscillator, which generates an output clock. The frequency locked loop is responsive to pure offset information obtained from the incoming synchronization packets. A transient phase adjuster extracts information from the incoming synchronization packets taking into account transit delays to effect fast frequency adjustment of the control input and to provide a phase adjustment input to the frequency locked loop. A secondary phase path is selectable in response to de-activation of the transient phase adjuster to provide a phase correction to the control input derived from said pure offset information when the transient phase adjuster is inactive.