Clock Recovery PLL Using Internal References for Low-Jitter Locking
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Solution Overview
Problem
Existing clock and data recovery (CDR) solutions in communication systems require additional control loops, external reference clock sources, and are prone to jitter, lack of robust frequency acquisition, and imprecise phase locking, increasing cost, complexity, and size.
Innovation Solution
A single control loop phase-locked loop circuit arrangement that derives a common reference signal from either of two internal reference signals, eliminating the need for an external clock source and utilizing different bandwidths in various modes to enhance synchronization and reduce jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple control loops are used for CDR, then frequency acquisition robustness is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple control loops into a single control loop that dynamically adjusts its characteristics. The phase-locked loop (PLL) integrates both coarse frequency acquisition and fine phase locking functions that were previously separated into multiple loops, reducing device complexity while maintaining frequency acquisition robustness through adaptive bandwidth control.
Solution Approach 2:
The patent implements dynamic bandwidth adjustment in the single control loop. The loop bandwidth is adaptively changed based on operating conditions - wider bandwidth during frequency acquisition for robustness, and narrower bandwidth during phase locking for precision. This dynamic behavior replaces the need for multiple static control loops.
2Measurement precision
If external reference clock sources are used, then phase locking precision is improved, but cost increases
Solution Approach 1:
The patent implements self-service by deriving the reference signal from the input data stream itself rather than requiring an external reference clock source. The control unit extracts timing information from the incoming signal and uses it to generate the reference signal for the PLL, eliminating external components while maintaining phase locking precision through adaptive synchronization.
Solution Approach 2:
The control unit performs multiple functions: it derives the reference signal from the input stream, generates control signals for the PLL, and adjusts loop parameters dynamically. This multi-functional approach replaces what would traditionally require separate external reference sources and control circuitry, reducing cost and complexity.
3Device complexity
If a single control loop is used, then device complexity is reduced, but frequency acquisition robustness deteriorates
Solution Approach 1:
The patent changes the bandwidth parameter of the control loop dynamically during operation. During frequency acquisition, the loop bandwidth is set to a wider value to improve robustness and speed of acquisition. During phase locking, the bandwidth is narrowed for higher precision. This parameter adaptation within a single loop achieves what previously required multiple loops with fixed parameters.
Solution Approach 2:
The patent employs periodic switching between different operational modes (frequency acquisition mode and phase locking mode) with corresponding bandwidth adjustments. This periodic adaptation of control characteristics enables a single loop to perform the sequential functions that traditionally required multiple concurrent loops, maintaining robustness while reducing complexity.
4Device complexity
If external oscillators are eliminated, then cost is reduced, but jitter increases
Solution Approach 1:
The patent implements feedback control where the PLL continuously monitors the phase and frequency of the recovered clock signal and adjusts its output accordingly. This closed-loop feedback mechanism compensates for jitter and timing variations that would normally require external oscillators to suppress, maintaining signal quality while eliminating external components.
Solution Approach 2:
The patent replaces the mechanical/physical external oscillator system with an electronic software-controlled PLL system. The reference signal is generated and adjusted electronically based on digital control algorithms, eliminating the need for physical external oscillators while maintaining or improving timing accuracy through adaptive electronic control.
Data Source
AI summary
A circuit arrangement for clock and data recovery comprises a control unit, a phase-locked loop circuit and a sampling unit. The control unit is configured to derive a first reference signal and a second reference signal from an input signal. Furthermore, the control unit is configured to derive a common reference signal from one of the first reference signal and the second reference signal, selected depending on a mode of operation of the circuit arrangement. The phase-locked loop circuit is configured to generate an oscillator signal based on the common reference signal. The sampling unit is configured to extract a recovered data signal from the input signal.