Clock Recovery Phase Path With Speculative Parallel Selection
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Solution Overview
Problem
Conventional clock and data recovery (CDR) circuits experience significant latency, which affects system performance, as they require multiple cycles to complete a CDR operation and generate phase selection signals, leading to increased internal delay.
Innovation Solution
The implementation of a CDR circuit with a phase path that includes speculative and parallel computations, where phase detection and speculative calculation circuits generate phase selection signals in parallel, reducing latency by allowing computations to be performed simultaneously with phase adjustment signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional CDR circuits use sequential processing to generate phase selection signals, then the circuit structure remains simple, but the latency increases and system performance deteriorates
Solution Approach 1:
The speculative calculation circuits perform phase selection signal generation in advance by speculating on potential phase adjustment signal values. Multiple speculative phase selection signals are generated before the actual phase adjustment signal is determined, allowing the circuit to skip waiting time and reduce overall latency.
Solution Approach 2:
The phase selection signal generation process is divided into multiple parallel speculative calculation paths, each handling different potential phase adjustment scenarios. This segmentation allows simultaneous processing of multiple possibilities rather than sequential processing, significantly reducing the time to determine the final phase selection signal.
2Speed
If conventional CDR circuits process phase detection and phase selection sequentially, then the circuit design remains straightforward, but the internal delay increases
Solution Approach 1:
The speculative calculation circuits compute potential phase selection signals in advance based on assumed phase adjustment values. This preliminary computation occurs parallel to the phase detection process, so when the actual phase adjustment signal is determined, the corresponding phase selection signal is already available or can be quickly selected from pre-computed options.
Solution Approach 2:
The circuit dynamically selects which speculative phase selection signal to use based on the actual phase adjustment signal determined by the phase detection circuit. The selection circuit chooses from multiple pre-computed speculative results, adapting the output to match the actual operating conditions without requiring re-computation.
3Reliability
If multiple CDR operation cycles are used to complete phase selection, then computational accuracy is maintained, but the time required for synchronization increases
Solution Approach 1:
Multiple speculative phase selection signals are computed in advance for different potential phase adjustment scenarios. This preliminary computation ensures that accurate phase selection is ready beforehand, eliminating the need for multiple sequential operation cycles and reducing synchronization time while maintaining accuracy.
Solution Approach 2:
The phase detection circuit provides feedback on the actual phase adjustment signal, which is then used to select the correct phase selection signal from the pre-computed speculative results. This feedback mechanism ensures that the final phase selection is accurate while avoiding the need for iterative re-computation cycles.
Data Source
AI summary
Clock data recovery can be accomplished using a phase path circuit that is configured to receive a data signal and a clock signal. A phase detection circuit detects phase differences between the data signal and a plurality of clock signals and generates a phase adjustment signal based upon a majority voting of the detected phase differences. Speculative calculation circuits generate speculative phase selection signals. Selection circuits select, in response to the phase adjustment signal, from speculative phase selection signals to provide outputs of the phase path circuit.