Clock Recovery Circuit with Staged Phase Adjustment for Jitter Tolerance
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Solution Overview
Problem
The jitter tolerance of clock and data recovery circuits in memory storage devices is reduced when there is a large phase or frequency difference between data and clock signals, leading to inefficiencies in signal correction and jitter suppression.
Innovation Solution
A clock and data recovery circuit comprising a phase detector, voter circuit, digital loop filter, and phase interpolator, where the voter circuit operates at a first clock frequency and the digital loop filter operates at a second clock frequency, generating adjustment signals to sequentially adjust the clock signal and improve jitter tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the phase difference or frequency difference between data signal and clock signal is relatively large, then the clock and data recovery circuit can detect and correct the signals, but the jitter tolerance of the circuit is reduced due to overly large sudden adjustment on phase or frequency
Solution Approach 1:
The patent divides the adjustment process into multiple stages by introducing a first adjustment amount and a second adjustment amount, where the first adjustment amount is applied initially and the second adjustment amount is applied subsequently. This segmentation allows the circuit to handle large phase or frequency differences without causing excessive jitter, as the adjustment is distributed across multiple smaller steps rather than applied all at once.
Solution Approach 2:
The patent applies a preliminary adjustment using the first adjustment amount before applying the final adjustment using the second adjustment amount. This preliminary action reduces the initial large phase or frequency difference to a smaller residual difference, which can then be corrected with finer adjustment, thereby maintaining jitter tolerance while still achieving accurate signal recovery.
2Speed
If transmission frequency of the data signal increases, then the data transmission capability improves, but the clock correction efficiency and jitter suppression of the clock and data recovery circuit become more critical and harder to maintain
Solution Approach 1:
The patent employs dynamic adjustment by determining adjustment amounts based on the detected phase difference and frequency difference. The first adjustment amount and second adjustment amount are dynamically selected according to the magnitude of the detected differences, allowing the circuit to adapt to varying transmission frequencies and signal conditions while maintaining effective clock correction and jitter suppression.
Solution Approach 2:
The patent changes the adjustment parameters (first adjustment amount and second adjustment amount) based on the detected phase and frequency differences. By adjusting these parameters dynamically, the circuit can maintain optimal correction efficiency across different transmission frequencies, ensuring that jitter suppression remains effective even as data transmission frequency increases.
Data Source
AI summary
A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.