Clock Recovery from Digital Signals Using Strobe Pulses
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Solution Overview
Problem
Existing automatic test equipment (ATE) faces challenges in accurately measuring the timing of semi-conductor chips due to signal slewing and jitter, especially when testing high-speed signals, and is impractical to access a device's synchronous internal clock without tying up valuable hardware channels.
Innovation Solution
A method and apparatus that generates strobe pulses with incrementally increasing delay values to capture samples of digital signals, encodes edge times and polarities, and uses an accumulator to average these values, allowing for the extraction of a clock signal from a digital signal without direct comparison to the system clock, thereby reducing the impact of slewing and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a test system clock is used to test data on buses having a synchronous clock, then timing measurements can be performed, but data on the bus may have very high jitter relative to the test system clock
Solution Approach 1:
The patent creates a copy of the DUT clock signal by using the DUT's own synchronous clock to generate a test system clock that matches the DUT clock frequency and phase. This copied clock signal is then used for timing measurements, eliminating jitter issues because the measurement clock is synchronized to the data clock rather than being an independent external clock.
Solution Approach 2:
The patent introduces an intermediary process where the DUT's synchronous clock acts as a mediator between the data signals and the test system. The synchronous clock is used to generate the test system clock, creating an intermediate reference that bridges the data domain and the measurement domain, thereby eliminating direct jitter comparison issues.
2Measurement precision
If the DUT's synchronous internal clock is accessed for timing measurements, then accurate relative timing can be measured, but valuable test system hardware channels are tied up
Solution Approach 1:
The patent enables the DUT to serve itself by using its own synchronous clock to generate the test system clock. This self-service approach eliminates the need for external clock distribution hardware, as the DUT's internal clock resource is utilized to create the measurement reference, thereby freeing up valuable test system hardware channels while maintaining accurate timing measurements.
3Speed
If signal slewing and jitter are present in high-speed signals, then data transmission occurs, but measurement results become inaccurate
Solution Approach 1:
The patent implements a feedback mechanism where the DUT's synchronous clock, which is inherently synchronized to the high-speed data transmission, is used to generate the test system clock. This feedback from the actual data clock signal ensures that the measurement reference automatically tracks and compensates for slewing and jitter effects, maintaining measurement accuracy even at high transmission speeds.
Data Source
AI summary
A method and apparatus is provided to recover clock information embedded in a digital signal such as a data signal. A set of strobe pulses can be generated by routing an edge generator to a delay elements with incrementally increasing delay values. A set of latches triggered by incrementally delayed signals from the edge generator can capture samples of the data signal. An encoder can convert the samples to a word representing edge time and polarity of the sampled signal. The word representing edge time can be stored in memory. An accumulator can collect the average edge time over N samples. The average edge time can be adjusted with a fixed de-skew value to form the extracted clock information. The extracted clock information can be used as a pointer to the words stored in memory.