Clock Recovery Circuit Using Transition Detection Without Jitter Compensation
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Solution Overview
Problem
Existing signal receiving devices require additional circuits to account for jitter characteristics in the received signal, which complicates the recovery of data and clock signals and increases device size.
Innovation Solution
A signal receiving device that recovers data and clock signals without considering jitter characteristics, utilizing a transition detecting device and a clock data recovering device to generate a recovery clock signal based on differential signals and comparison signals, and a calibration device to adjust gain control signals, thereby eliminating the need for additional jitter adjustment circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuits are added to account for jitter characteristics in the received signal, then the reliability of clock and data recovery is improved, but the device complexity and size increase
Solution Approach 1:
The patent extracts and eliminates the jitter compensation function from the signal receiving device. By determining that jitter characteristics do not need to be considered for clock and data recovery in the C-PHY interface, the patent removes the additional jitter adjustment circuits that would otherwise be required, thereby reducing device complexity while maintaining recovery reliability
Solution Approach 2:
The transition detecting device and clock data recovering device are designed to perform multiple functions simultaneously - detecting transitions between signal levels, recovering clock signals, and recovering data signals - without requiring separate dedicated circuits for each function or for jitter compensation, thus reducing overall device complexity
2Measurement precision
If additional circuits are added to account for jitter characteristics, then the precision of clock recovery is improved, but the area of the device increases
Solution Approach 1:
The patent removes the jitter compensation circuits from the device architecture by determining that they are not necessary for achieving precise clock recovery in the C-PHY interface context, thereby reducing device area while maintaining clock recovery precision
Solution Approach 2:
The patent uses simplified transition detection based on comparing signal levels at discrete time points, which effectively captures the essential clock information without requiring complex jitter compensation circuits, achieving precise clock recovery with reduced device area
3Manufacturing precision
If the signal receiving device considers jitter characteristics, then the accuracy of data recovery is improved, but the device complexity increases
Solution Approach 1:
The patent extracts the jitter compensation functionality from the data recovery process by determining that it is unnecessary for achieving accurate data recovery in the C-PHY interface, thereby simplifying the signal processing complexity while maintaining data recovery accuracy
Solution Approach 2:
The clock data recovering device uses the transition detection signals directly to control the timing of data sampling, allowing the system to self-adjust to signal variations without requiring external jitter compensation circuits, thus maintaining accuracy while reducing complexity
Data Source
AI summary
A signal receiving device may not need to consider jitter characteristics of a received signal by including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.