Clock Data Recovery Circuit With Multi-Band VCO Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Display devices face challenges in rapidly generating a clock signal with appropriate frequency corresponding to various data supply speeds, leading to prolonged time for the driver unit to produce a clock signal with the necessary frequency.
Innovation Solution
A clock data recovery circuit is designed with a phase detector, charge pump, switches, voltage control oscillators, and an oscillator controller, which includes specific configurations and operations to generate a clock signal efficiently, such as non-overlapping switch periods and frequency band management, allowing for rapid clock signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single voltage control oscillator is used to cover a wide frequency range, then the device complexity is reduced, but the time to generate a clock signal at the required frequency increases significantly
Solution Approach 1:
The frequency range is divided into multiple sub-ranges, with each voltage control oscillator responsible for a specific sub-range. The oscillator controller selects and activates only the oscillator whose frequency range matches the required clock frequency, enabling rapid clock signal generation without requiring a single oscillator to cover the entire wide range.
2Loss of time
If multiple voltage control oscillators with different frequency ranges are used, then the clock signal generation time is reduced, but the device complexity increases
Solution Approach 1:
The oscillator controller dynamically selects and activates the appropriate voltage control oscillator based on the required clock frequency. This dynamic selection mechanism allows the system to adapt to different frequency requirements in real-time, maintaining rapid response while managing complexity through intelligent control rather than hardware redundancy.
Solution Approach 2:
The voltage control oscillators are pre-configured with specific frequency ranges, and the oscillator controller pre-determines which oscillator to activate based on the required frequency. This preliminary configuration and selection process eliminates the need for gradual frequency tuning, enabling immediate clock signal generation at the required frequency.
3Adaptability or versatility
If the data supply speed varies widely, then the adaptability of the display device is improved, but the time to adjust the clock signal frequency increases
Solution Approach 1:
The frequency adaptation process is segmented into two stages: first, the oscillator controller quickly selects the appropriate voltage control oscillator based on the required frequency range; second, the phase detector and charge pump perform fine-tuning within that range. This segmented approach enables rapid adaptation to widely varying data supply speeds while maintaining frequency precision.
Data Source
AI summary
A clock data recovery circuit includes the following elements: a phase detector for outputting a phase adjustment signal by comparing a clock signal of a first node and an input signal; a charge pump for adjusting a charge amount of a second node according to the phase adjustment signal; a first switch including one end coupled to the second node and including another end coupled to a third node; a second switch including one end which receives a bias voltage and including another end coupled to the third node; a capacitor including a first electrode coupled to the third node; third switches; and voltage control oscillators including control terminals coupled to the third node and including output terminals coupled to the first node through the third switches.