Clock Data Recovery Using Wide-Pulse Phase Detection
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Solution Overview
Problem
Conventional clock data recovery apparatuses become unstable at high frequencies due to narrow pulse widths of increment and decrement signals, leading to locking failures in high-speed communication systems.
Innovation Solution
A clock data recovery apparatus that uses a phase locked loop unit to output multiple clock signals with lower frequencies, a voltage control delay line to adjust clock signals based on input voltage, a phase detection unit to generate wider pulse width increment and decrement signals, and a loop filter to control delay, ensuring stable operation by maintaining a constant control voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to meet high-speed communication requirements, then the data transmission speed is improved, but the pulse width of increment and decrement signals becomes narrow causing locking failures
Solution Approach 1:
The phase detection process is segmented into multiple stages using different clock frequencies. A first phase detector operates at a lower clock frequency to generate wide pulse width increment and decrement signals for reliable locking, while a second phase detector operates at the higher data frequency for final synchronization. This segmentation allows each stage to optimize for its specific frequency range, resolving the contradiction between high-speed operation and stable locking.
2Speed
If a single high-frequency clock is used for data transmission, then the communication speed is improved, but the phase detection accuracy deteriorates due to narrow pulse widths
Solution Approach 1:
The invention introduces a frequency dimension to the phase detection process by using two different clock frequencies. The first phase detector uses a lower frequency (e.g., 1/4 or 1/8 of data frequency) to provide adequate pulse width for accurate phase detection and reliable locking. The second phase detector then operates at the full data frequency to maintain high-speed communication. This dimensional approach to frequency selection resolves the contradiction between speed and measurement precision.
Data Source
AI summary
A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.