Clock Recovery Circuit With Adaptive Window Timing for High-Speed Serial Data
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Solution Overview
Problem
In high-speed serial data communication, receiving circuits face challenges in accurately capturing serial data due to shortened unit intervals, making it difficult to synchronize data and clock signals, especially as data transmission rates increase.
Innovation Solution
A clock data recovery circuit that includes a clock recovery circuit, a delayed locked loop circuit, and a window generating circuit to accurately recover a clock and data from an input data signal by generating recovery clock signals, detecting unit intervals, and synchronizing window signals, thereby improving data transmission speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission rate is increased, then productivity is improved, but measurement precision deteriorates due to shortened unit interval making it difficult to accurately capture data bits
Solution Approach 1:
The patent applies preliminary action by generating window signals in advance of the actual data sampling point. The window signal is generated based on a delayed version of the recovered clock signal, positioned to precede the center of the unit interval. This allows the sampling circuit to know in advance when to capture the data bit, ensuring accurate timing even at high transmission rates where the unit interval is shortened.
2Device complexity
If conventional clock recovery methods are used, then device complexity is kept simple, but reliability deteriorates due to inability to maintain accurate synchronization independent of process voltage temperature and transmission rate variations
Solution Approach 1:
The patent applies dynamics by making the window signal generation adaptive to timing variations. The window signal is generated based on a delayed clock signal whose delay is optimized to account for process voltage temperature (PVT) variations and transmission rate changes. This dynamic adjustment of the window signal timing ensures that the sampling point remains accurately positioned within the unit interval regardless of operating conditions.
3Measurement precision
If accurate data capture is achieved through complex synchronization methods, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies the taking out principle by extracting only the essential timing information needed for accurate sampling. Instead of using complex multi-stage synchronization circuits, the invention extracts the core timing relationship by generating a window signal from a delayed clock signal. This window signal contains all the necessary timing information to position the sampling point accurately, simplifying the overall circuit while maintaining high measurement precision.
Data Source
AI summary
A method of recovering a clock and data from an input data signal including an embedded clock, the method including generating a recovery clock signal from the input data signal based on a first window signal; detecting a unit interval corresponding to one bit of the input data signal based on the recovery clock signal; delaying a signal synchronized with the recovery clock signal based on the unit interval; and generating the first window signal based on the delayed signal.