Clock Data Recovery Circuit Without an External Crystal Oscillator
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Solution Overview
Problem
Conventional clock and data recovery circuits require external crystal oscillators, which are expensive and occupy significant space, making them costly and bulky, while also having limitations in frequency error tolerance, especially in applications like USB 3.0 where the frequency error between the reference clock and input data stream must be within a specific range.
Innovation Solution
A clock and data recovery circuit that generates a reference clock based on the input data stream using a phase detector, integration modules, an operation unit, an oscillation circuit, and a phase converter, eliminating the need for an external crystal oscillator, thereby reducing fabrication costs and circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an external crystal oscillator is used to generate the reference clock, then the frequency error can be kept within specification (less than 300 ppm), but the fabrication cost increases and the circuit board space occupation increases
Solution Approach 1:
The system uses the input data stream itself as the reference clock source through a feedback mechanism. The phase detector compares the input data stream with the recovered clock signal, and the voltage-controlled oscillator adjusts its output frequency based on the phase difference, making the system self-regulating and eliminating the need for external crystal oscillators
Solution Approach 2:
A voltage-controlled oscillator is introduced as an intermediary component that can dynamically adjust its output frequency based on control voltage from the phase detector, serving as a flexible reference clock source that replaces the rigid external crystal oscillator while maintaining frequency accuracy within specifications
2Manufacturing precision
If an external crystal oscillator is used to generate the reference clock, then the frequency error can be kept within specification, but the circuit board space occupation increases
Solution Approach 1:
The system uses the input data stream itself as the reference clock source through a feedback mechanism. The phase detector compares the input data stream with the recovered clock signal, and the voltage-controlled oscillator adjusts its output frequency based on the phase difference, making the system self-regulating and eliminating the need for external crystal oscillators
Solution Approach 2:
The reference clock generation function is merged with the data recovery process itself. The voltage-controlled oscillator's output serves dual purposes: as the reference clock for phase comparison and as the recovered clock signal, eliminating the need for separate external oscillator circuitry and reducing board space
3Reliability
If the frequency error between reference clock and input data stream is strictly controlled (within 300 ppm), then data recovery correctness is ensured, but the system becomes more sensitive to frequency variations and requires expensive crystal oscillators
Solution Approach 1:
The system transitions from a static frequency reference (crystal oscillator) to a dynamic frequency source (voltage-controlled oscillator) that can automatically adjust its output frequency in real-time based on feedback from the phase detector, allowing the system to adapt to frequency variations while maintaining data recovery correctness
Solution Approach 2:
A feedback loop is established where the phase detector continuously compares the input data stream with the voltage-controlled oscillator's output and adjusts the oscillator's frequency based on the phase difference, enabling the system to maintain reliability while being tolerant of initial frequency variations up to 300 ppm
Data Source
AI summary
A clock and data recovery (CDR) circuit having a phase locked module and a frequency locked module is provided. A phase detector of the phase locked module compares a phase of an input data stream with a phase of a data-recovery clock to output an adjusting signal. The frequency locked module performs a first-order integration process and a second-order integration process on the adjusting signal to generate a first integration error and a frequency control signal. The phase locked module generates a phase control signal according to the first integration error and the adjusting signal. An oscillation circuit of the frequency locked module generates at least one reference clock according to the frequency control signal. A phase converter of the phase locked module outputs the data-recovery clock to the phase detector according to the phase control signal and the reference clock.