Clock Regeneration Circuit for Multi-Level FSK Signals
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Solution Overview
Problem
Conventional clock regeneration methods fail to accurately regenerate a stable clock from multi-level modulated waves, especially in narrow band communication scenarios, due to deviations in timing caused by phase differences and increased calculation complexity.
Innovation Solution
A clock regeneration circuit that employs oversampling and a timing correction mechanism, using a quaternary FSK symbol regeneration circuit with a synchronization-word-pattern detection circuit to adjust the symbol clock timing and correct DC offsets, allowing for stable clock regeneration with reduced calculation complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional clock regeneration methods are used for multi-level modulated waves, then clock regeneration can be performed, but timing accuracy deteriorates due to phase differences and Nyquist criterion violations
Solution Approach 1:
The patent employs a feedback mechanism where the regenerated clock signal is continuously monitored and compared against the original timing reference. Phase detectors detect timing deviations and feed correction signals back to adjust the clock phase, ensuring continuous timing accuracy despite phase differences and Nyquist criterion violations in narrow band communication
Solution Approach 2:
The patent changes the operating parameters of the clock regeneration circuit by adjusting the center frequency of the band-pass filter and modifying the phase detection thresholds. These parameter adjustments allow the system to adapt to different modulation schemes and communication conditions, maintaining timing accuracy across varying scenarios
2Measurement precision
If phase correction is performed using zero cross point detection, then phase difference can be corrected, but calculation complexity increases
Solution Approach 1:
The patent extracts only the essential timing information from the modulated signal by using band-pass filtering to isolate the clock component frequency. This extraction approach eliminates the need for complex full-signal analysis, reducing calculation complexity while maintaining phase correction accuracy through simplified zero cross point detection
Solution Approach 2:
The patent performs preliminary filtering and signal conditioning before phase detection. By pre-processing the signal through band-pass filtering and amplitude adjustment, the system prepares the signal in advance, making the subsequent phase correction calculation simpler and more efficient
3Measurement precision
If oversampling is performed to improve clock regeneration accuracy, then timing precision improves, but calculation amount increases
Solution Approach 1:
The patent applies partial oversampling rather than full oversampling across the entire signal processing chain. By selectively oversampling only at critical detection points and using interpolation for intermediate values, the system achieves improved timing precision without proportionally increasing the overall calculation burden
Data Source
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Figure 3A~3B
AI summary
Provided are a clock regeneration circuit and a receiver, wherein difference values (V1, V2, V3) from an ideal value can be obtained for respective three sample data (T1, T2, T3) which are obtained by oversampling a 4-level FSK demodulated signal at a higher frequency than that of a symbol clock and in which sample data (T2) at a symbol point (P) is included at a median, and a sampling timing of the symbol point (P) is shifted toward a point where the sample data (T3) having a smaller difference value is obtained, by a time corresponding to the difference value (V2) at the symbol point. Thus, the clock regeneration circuit and the receiver are capable of regenerating a stable clock from multi-level modulated waves in a small calculation amount.