Clock Regeneration Circuit for PWM Demodulation With Fewer Polyphase Clocks
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Solution Overview
Problem
The existing photocoupler type insulating devices require a large number of polyphase clock signals to demodulate digital data, leading to increased circuit area and power consumption, making it difficult to reduce the size and power consumption of the receiving circuit.
Innovation Solution
A clock regeneration circuit that generates a clock signal with a prescribed period and duty cycle using a D flip-flop circuit, delay circuit, comparator, and feedback circuit, allowing for efficient demodulation of digital data with reduced polyphase clock signals, thereby minimizing circuit area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay-locked loop circuit and demodulation circuit are integrated to regenerate clock signals for PWM signal demodulation, then the clock signal can be regenerated and digital data can be demodulated, but the circuit area and power consumption are increased
Solution Approach 1:
The patent extracts and eliminates redundant circuits from the integrated DLL-demodulation system. Specifically, it removes unnecessary delay elements and simplifies the demodulation circuitry while retaining the core functionality of clock regeneration and PWM demodulation, thereby reducing circuit area without compromising reliability
Solution Approach 2:
The patent changes key parameters of the clock regeneration circuit, including optimizing the delay time constants and adjusting the operating point of the circuit components. These parameter optimizations allow the circuit to achieve reliable clock regeneration with fewer components, thus reducing the overall circuit area
2Reliability
If a delay-locked loop circuit and demodulation circuit are integrated to regenerate clock signals for PWM signal demodulation, then the clock signal can be regenerated and digital data can be demodulated, but the power consumption is increased
Solution Approach 1:
The patent removes redundant active elements and feedback paths from the integrated circuit that contribute to power consumption. By eliminating unnecessary delay stages and simplifying the demodulation logic, the circuit achieves reliable operation with significantly reduced power draw
Solution Approach 2:
The patent implements a simplified version of the full DLL circuit that provides sufficient clock regeneration accuracy for the application without the complete set of delay elements. This partial implementation reduces power consumption while maintaining adequate reliability for PWM demodulation
3Measurement precision
If a large number of polyphase clock signals are used to demodulate multibit PWM digital data, then accurate demodulation can be achieved, but the circuit area and power consumption are increased
Solution Approach 1:
The patent makes a single polyphase clock signal serve multiple functions by using it for both clock regeneration and demodulation of multiple data bits. The circuit is designed to extract maximum information from fewer clock phases through sophisticated sampling and reconstruction algorithms, thereby reducing the total number of polyphase clocks needed while maintaining demodulation accuracy
Solution Approach 2:
The patent transitions from using multiple clock phases in the time domain to utilizing amplitude and phase modulation dimensions for encoding multiple bits. By moving the information encoding to additional signal dimensions rather than relying solely on multiple clock phases, the circuit achieves accurate demodulation with fewer polyphase clocks
Data Source
AI summary
A clock regeneration circuit includes: a signal input terminal; a D flip-flop circuit; a reset signal generation circuit; a delay circuit; a comparator; a first capacitor; and a feed back circuit. The signal input terminal is inputted with a pulse width modulation signal. The D flip-flop circuit includes a clock terminal, an output terminal, and a reset terminal. The reset signal generation circuit is configured to input a reset signal generated in synchronization with the pulse width modulation signal to the reset terminal at a first time. The delay circuit is configured to delay the pulse width modulation signal. The feedback circuit includes a current source having a control terminal. The feedback circuit is configured to change one of charge rise time and discharge fall time in response to the signal of the comparator to control duty cycle of the signal of the comparator.