Digital Clock Control Register for Faster FLL Locking
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Solution Overview
Problem
Current Frequency-Locked Loops (FLL) and other clock signal generating circuits face challenges in reducing the number of steps for storing digital control information and extending the lock time, which prolongs the recovery from sleep mode to active mode due to the need for binary search algorithms and multiple steps in setting delay stages.
Innovation Solution
A semiconductor integrated circuit with a digital control clock signal generating part that includes a comparator, counter, and control register, where the control register stores two or more bits of digital control information, and a control data storing circuit that pre-stores initial set data for operation conditions, allowing direct selection of operation conditions to reduce the number of steps and lock time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If binary search algorithm is used to set delay stages in FLL, then accurate frequency locking is achieved, but the number of steps increases and lock time is prolonged
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing optimal delay stage values in a lookup table before operation. When frequency locking is needed, the system directly retrieves the pre-computed delay value corresponding to the target frequency, eliminating the need for time-consuming binary search algorithms during actual lock operations. This significantly reduces lock time while maintaining accurate frequency locking.
Solution Approach 2:
The patent segments the frequency locking process into two distinct phases: a pre-computation phase where delay values are calculated and stored in a lookup table, and an operation phase where values are directly retrieved. This segmentation allows the system to perform complex calculations beforehand when time is not critical, and execute simple retrieval operations when speed is essential, thereby resolving the contradiction between accuracy and speed.
2Reliability
If multiple steps are used to store digital control information in control register, then accurate control is achieved, but the complexity of control steps increases
Solution Approach 1:
The patent applies preliminary action by pre-determining and storing the relationship between frequency division ratios and optimal delay stage values in a lookup table during design or initialization. This eliminates the need for complex multi-step control sequences during operation, as the system can directly retrieve the required control value from the pre-prepared table, simplifying the control process while maintaining accuracy.
Solution Approach 2:
The patent uses copying by storing pre-computed control values in a lookup table that can be quickly referenced. Instead of recalculating or sequentially determining control parameters during operation, the system copies the appropriate pre-stored value from the lookup table based on the current frequency division ratio, thereby simplifying control steps while ensuring accurate control.
3Device complexity
If FLL is used for clock signal generation, then circuit complexity is reduced compared to PLL, but lock time is prolonged due to lack of phase locking
Solution Approach 1:
The patent applies preliminary action by pre-calculating delay stage values that correspond to different frequency division ratios and storing them in a lookup table. When the FLL needs to lock to a new frequency, the system directly retrieves the pre-computed delay value instead of performing time-consuming iterative adjustments. This maintains the simple FLL circuit structure while dramatically reducing lock time.
Solution Approach 2:
The patent changes the control parameter from iterative adjustment to direct table lookup. By storing the relationship between frequency division ratios and optimal delay stages in advance, the system can instantly switch between different operating frequencies by simply changing the retrieved parameter value, thereby reducing lock time without increasing circuit complexity.
Data Source
AI summary
The semiconductor integrated circuit includes a clock generating section having a digital control signal generating part operable to generate a clock signal and a digital control part. The clock generating section further includes a phase-frequency comparator and a control register. The comparator is supplied with a reference signal CLKin and a feedback signal. The control register is supplied with an output signal of the comparator, and stores two or larger bits of digital control information. The clock generating section further includes a control data storing circuit for previously storing sets of initial set data for lock operations. In response to operation select information, initial set data are stored at upper bit of the control register from the control data storing circuit. Thus, it becomes possible to reduce the number of steps to store control information in a register for digitally controlling the clock signal generating part.