Clock Generator Re-Lock Control After Low-Power Frequency Drift
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Solution Overview
Problem
In systems-on-a-chip (SoCs), clock signal generators may experience frequency drift when disabled or in reduced power states, leading to delays and increased power consumption when recalibrating upon re-enablement, affecting performance.
Innovation Solution
A clock generation unit that adjusts its output frequency upon re-enablement based on a predetermined time and comparison with a target frequency, using a variable oscillator and comparison circuit to quickly reacquire lock, even when the SoC is in reduced power states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the clock signal generator is disabled to reduce power consumption, then power consumption is reduced, but the clock signal loses synchronization and requires recalibration time
Solution Approach 1:
The patent applies preliminary action by maintaining the clock generation unit in a low-power state with preserved calibration data rather than completely disabling it. The unit retains its last known good calibration state and can quickly resume operation without full recalibration, thus reducing the time loss while still achieving power savings.
Solution Approach 2:
The patent changes the operational parameters of the clock generation unit by introducing a reduced power state that preserves calibration data. This allows the unit to transition between full operation and low-power mode while maintaining synchronization accuracy, resolving the contradiction between power consumption and recalibration time.
2Reliability
If the clock signal generator operates continuously to maintain synchronization, then synchronization is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic action by allowing the clock generation unit to operate in full mode during active periods and transition to a reduced power state during inactive periods. The unit can quickly resume full operation when needed, maintaining synchronization reliability while reducing overall power consumption through periodic low-power states.
Solution Approach 2:
The patent changes the operational parameters by introducing a reduced power state that maintains synchronization capability with lower energy consumption. This parameter change allows the system to maintain reliability during active use while reducing power consumption during idle periods, resolving the contradiction between synchronization accuracy and power consumption.
3Productivity
If the clock signal generator quickly resumes operation after disabling, then productivity is improved, but frequency drift occurs
Solution Approach 1:
The patent applies preliminary action by preserving calibration data in the reduced power state. This allows the clock generation unit to quickly resume operation with minimal frequency drift, as the last known good calibration is retained. The unit can perform a quick frequency adjustment rather than a complete recalibration, thus improving response speed while maintaining frequency accuracy.
Solution Approach 2:
The patent changes the operational parameters by maintaining calibration data during reduced power state transitions. This parameter preservation enables the unit to quickly resume with accurate frequency, resolving the contradiction between response speed and frequency accuracy by ensuring calibration information is retained across power states.
Data Source
AI summary
Various embodiments of a clock generator are disclosed. An example system may include a functional unit, and a clock generation unit configured to adjust a frequency of an output clock signal responsive to an assertion of an enable signal from the functional unit. The clock generation unit may also be configured to halt the output clock signal responsive to a de-assertion of the enable signal by the functional unit and to restart the output clock signal responsive to a determination that a first predetermined amount of time has elapsed since the output clock signal was halted. The clock generation unit may be further configured to adjust the frequency of the output clock signal responsive to restarting the output clock signal, and to halt the output clock signal responsive to a determination that the frequency of the output clock signal is within a predetermined frequency range that includes the target frequency.