Clock Synchronization Relocking With DFFs for Low-Jitter Triggers
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Solution Overview
Problem
Existing clock synchronization systems in superconducting quantum computers suffer from high jitter in trigger signals, leading to synchronization challenges and reduced precision in signal synchronization.
Innovation Solution
A system and method that utilizes a quantum control processor (QCP) to generate a signal for global synchronization, which is then processed through frequency conversion and signal synchronization modules with D flip-flops (DFFs) to achieve low-jitter target clock signals, reducing signal delay and improving synchronization precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a trigger signal is independently generated from a module and transmitted via coaxial cables to synchronize multiple ADC or DAC modules, then signal synchronization across modules is achieved, but the trigger signal exhibits high jitter leading to synchronization inaccuracy
Solution Approach 1:
The patent introduces a clock chip as an intermediary device to generate the trigger signal, replacing the conventional module-based independent generation method. The clock chip serves as a central mediator that provides a stable, low-jitter trigger signal to all ADC and DAC modules through coaxial cables, thereby improving synchronization precision while maintaining system reliability
Solution Approach 2:
The patent replaces the conventional electronic trigger signal generation method (using FPGA or module internal generators) with a dedicated clock chip-based system. This substitution introduces a specialized device optimized for low-jitter signal generation, effectively reducing trigger signal jitter and improving overall synchronization accuracy
2Adaptability or versatility
If the trigger signal is generated by an FPGA chip, then signal generation flexibility is achieved, but the trigger signal has high jitter compared to a clock chip
Solution Approach 1:
The patent positions the clock chip as an intermediary between the control system and the ADC/DAC modules, specifically for trigger signal generation. While FPGA maintains its role for flexible control logic, the clock chip dedicatedly handles trigger signal generation, combining the advantages of both approaches: FPGA provides adaptability while the clock chip ensures precision
3Stability of the object's composition
If coaxial cables of identical lengths are used to transmit trigger signals to multiple modules, then signal transmission consistency is achieved, but signal delay and synchronization accuracy are still limited by trigger signal jitter
Solution Approach 1:
The patent extracts the trigger signal generation function from the modules themselves and concentrates it in a dedicated clock chip. By separating the trigger generation function from the modules and using identical-length coaxial cables for transmission, the system achieves both transmission consistency and reduced jitter-induced delays
Solution Approach 2:
The clock chip acts as a central intermediary that generates synchronized trigger signals and distributes them through identical-length coaxial cables to all modules. This intermediary approach ensures consistent transmission characteristics while minimizing the impact of cable length variations on synchronization accuracy
Data Source
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AI summary
A system for clock synchronization, including a quantum control processor (QCP) and digital-analog inter-converters. Each digital-analog inter-converter includes a frequency conversion module and a signal synchronization module. The signal synchronization module includes a D flip-flop (DFF). The QCP generates a signal for global synchronization (Sync_GLB) and reference clock signals (REFCLKs), and the Sync GLB and the corresponding REFCLK to the frequency conversion module, and transmits the Sync GLB to the signal synchronization module. The frequency conversion module performs frequency conversion on the REFCLK to obtain a target clock signal, generates an instruction for signal synchronization according to the signal for global synchronization, and transmits the instruction for signal synchronization and the target clock signal to the signal synchronization module. The signal synchronization module performs signal synchronization on the target clock signal via the DFF, based on the signal for global synchronization. The present disclosure further provides a method for controlling signal synchronization. The DFF relocks the signal for global synchronization to the target clock signal having a low jitter, reducing signal delay and improving precision of signal synchronization.