Clock Signal Reproduction Using Random-Walk Phase Slip Control
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Solution Overview
Problem
Conventional clock signal reproduction methods in wireless communication face challenges in accurately reproducing clock signals due to multi-path fading, leading to clock slips and phase fluctuations, which are difficult to correct quickly, especially when the phase difference between the reproduced clock signal and the internal clock signal exceeds a predetermined amount.
Innovation Solution
A clock signal reproduction device and method that includes an output clock oscillating section, an internal clock oscillating section, a data temporal lead/lag detecting section, and an inter-clock phase difference detecting section, which work together to detect phase shifts and cumulated time leads or lags, generating control signals to adjust the phase of the output clock signal and maintain it within a predetermined difference from the internal clock signal, thereby preventing clock slips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLL circuit phase control is used to reproduce clock signals, then the clock signal can be generated, but the phase control is slow and cannot quickly correct clock slips caused by multi-path fading
Solution Approach 1:
The patent divides the clock signal reproduction system into two independent oscillating sections: an output clock oscillating section that generates the output clock signal and an internal clock oscillating section that generates a stable reference. Each section operates independently with its own phase detection mechanism, allowing the output clock to respond quickly to phase shifts while the internal clock maintains long-term stability.
Solution Approach 2:
The patent introduces a temporal lead/lag detection section as an intermediary mechanism that detects phase differences between the data signal and output clock signal. This intermediary detection system enables quick identification of phase shifts without requiring the entire PLL circuit to re-lock, thus speeding up correction response.
2Measurement precision
If the monitoring period for detecting clock slips is extended to ensure accuracy, then detection precision improves, but the response time becomes too slow to prevent clock slips
Solution Approach 1:
The patent continuously monitors the temporal lead/lag between the data signal and output clock signal in advance, maintaining a ready state that detects phase shifts as they begin to develop. This preliminary detection allows the system to initiate correction before a full clock slip occurs, reducing both detection delay and correction time.
Solution Approach 2:
The patent implements a feedback mechanism where the temporal lead/lag detection section continuously provides phase difference information to the output clock oscillating section. This real-time feedback enables dynamic adjustment of the output clock phase, allowing the system to respond immediately to phase shifts while maintaining accurate detection through continuous monitoring.
3Reliability
If the pulse width of the VCO is adjusted to restrict error signal increase, then clock signal stability improves, but the method cannot quickly correct phase shifts or prevent clock slips
Solution Approach 1:
The patent makes the output clock oscillating section dynamically adjustable by introducing a temporal lead/lag detection mechanism that continuously monitors phase differences and automatically adjusts the output clock phase in response to detected shifts. This dynamic adjustment capability allows the system to quickly correct phase shifts while maintaining stability through controlled oscillation.
Data Source
AI summary
A phase comparator detects time lag or time lead of the phase of a data signal with respect to a reproduced clock signal from a first digital VCO. A random walk filter measures a difference between number of lags and number of leads, controls the first digital VCO to shift the phase of the reproduced clock signal in a direction to cancel the difference when the absolute value of the difference reaches a predetermined value, and resets the measurement result to restart the measurement. A phase comparator detects the phase difference between reproduced clock signals from the first digital VCO and a second digital VCO and notifies it to the random walk filter. While the amount of the notified phase difference is being a predetermined amount, the random walk filter neither resets the measurement result nor shifts the phase of the reproduced clock signal from the first digital VCO.