Clock Duty-Cycle Reset Signaling for Fewer Processor Output Pins
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional electronic devices require separate output terminals for clock and reset signals, increasing the number of terminals needed for data communication between a processor and an integrated circuit, which can lead to inefficiencies and potential electromagnetic interference.
Innovation Solution
A control device with a processor and a signal output circuit that outputs a clock signal with a predetermined duty ratio and switches to a lower duty ratio after communication ends, allowing the reset signal to be generated and stopped based on duty ratio changes, reducing the need for separate output terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate output terminals are used for clock signal and reset signal, then the integrated circuit can be reliably controlled, but the number of output terminals of the processor increases
Solution Approach 1:
The patent combines the clock signal output terminal and reset signal output terminal into a single shared terminal. The processor outputs both the clock signal and reset signal through the same terminal, reducing the total number of output terminals required while maintaining reliable control of the integrated circuit.
Solution Approach 2:
The patent dynamically changes the signal type output from the shared terminal based on timing. During the initial period, the terminal outputs a reset signal; after a predetermined time elapses, it switches to outputting a clock signal. This dynamic switching allows one terminal to serve multiple functions sequentially.
2Reliability
If multiple output terminals are used for data communication, then signal transmission is reliable, but power consumption increases
Solution Approach 1:
The patent merges the clock signal transmission function and reset signal transmission function into a single output terminal, thereby reducing the number of active terminals and lowering overall power consumption while maintaining reliable signal transmission for both functions.
Solution Approach 2:
The patent uses periodic action by outputting the reset signal for a predetermined time period and then switching to clock signal output. This time-based periodic control ensures that the reset function is performed reliably while minimizing the duration that multiple terminals are active, thus reducing power consumption.
3Reliability
If multiple output terminals are used for data communication, then signal transmission is stable, but electromagnetic interference increases
Solution Approach 1:
The patent combines multiple signal transmission functions into a single output terminal, thereby reducing the number of signal lines and minimizing electromagnetic interference between adjacent terminals while maintaining stable signal transmission for both reset and clock functions.
Solution Approach 2:
The patent dynamically switches the function of the shared terminal between reset signal output and clock signal output based on time. This dynamic allocation ensures that only one type of signal is transmitted at a time through the shared terminal, preventing electromagnetic interference between simultaneous signals while maintaining transmission stability.
Data Source
AI summary
A control device including a processor and a signal output circuit. The processor has an output terminal for outputting a clock signal, and executes data communication with an integrated circuit. The signal output circuit outputs a reset signal used for resetting the integrated circuit in response to an input of the clock signal having a predetermined first value of duty ratio after input of the clock signal to the integrated circuit, and stops output of the reset signal in response to switching of the duty ratio of the clock signal from the first value to a second value lower than the first value.