Clock and Reset Signal Management for Multi-Controller Power Sequencing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In systems with multiple controllers, ensuring that clock signals and reset cancellation signals are supplied in the correct order with power activation is crucial for normal operation, but existing technologies struggle with maintaining this order due to differences in power supply timing between controllers.

Innovation Solution

An information processing apparatus is designed with a first controller for device-independent control, a second controller for device-specific control, a clock management unit, and a reset cancellation management unit, all of which operate continuously to manage the supply of clock signals and reset cancellation signals, ensuring they are only enabled after power is supplied and clock signals start operating.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If power is supplied to multiple controllers simultaneously, then system startup is simplified, but clock signals and reset cancellation signals cannot be supplied in the correct order causing operational failure

Engineering Contradiction:
Improvepower supply procedureVSAvoidcontroller operation
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent applies preliminary action by having the clock management unit generate clock signals in advance based on power supply timing predictions, and the reset cancellation management unit prepare reset cancellation signals before power is actually supplied to controllers. This ensures that when power is supplied, the controllers receive signals in the correct order (clock first, then reset cancellation) without requiring complex sequential power supply procedures, thus simplifying operation while maintaining reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediary management units (clock management unit and reset cancellation management unit) that mediate between the power supply system and the controllers. These intermediaries buffer and coordinate the timing of clock and reset cancellation signals, ensuring correct signal delivery order regardless of power supply timing variations, thereby resolving the contradiction between simplified power supply and reliable controller operation

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If clock signals are supplied immediately with power, then controller activation is faster, but signals may be supplied before power is stable causing operational issues

Engineering Contradiction:
Improvecontroller activation speedVSAvoidsignal timing
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The clock management unit performs preliminary action by generating clock signals based on predicted power supply timing before the actual power is supplied to controllers. This allows the system to prepare timing-critical signals in advance, enabling fast controller activation while ensuring signals are ready and properly timed when power becomes stable, thus maintaining both speed and reliability

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11327522B2Information processing apparatus and circuit device
Publication Date: 2022.05.10 FUJIFILM BUSINESS INNOVATION CORP
  • US11327522B2 patent drawing
  • US11327522B2 patent drawing
  • US11327522B2 patent drawing

AI summary

An information processing apparatus includes a first controller that operates while receiving first power and executes device-independent control; a second controller that operates while receiving second power and controls a device on a basis of a command from the first controller; a clock management unit that operates while receiving continuous power, and limits supply of a first clock signal to the first controller until the first power is supplied and limits supply of a second clock signal to the second controller until the second power is supplied; and a reset cancellation management unit that operates while receiving continuous power, limits supply of a first reset cancellation signal to the first controller until operation using the first clock signal starts and limits supply of a second reset cancellation signal to the second controller until operation using the second clock signal starts.