Clock Resynchronization Circuit for High-Speed Data Transfer
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Solution Overview
Problem
Current communication systems face a limitation in clock signal frequency, restricting data transmission rates due to the upper frequency limit of circuit boards, which impedes the efficient interfacing of transmitter and receiver circuits.
Innovation Solution
A clock recovery circuit that adjusts the frequency of the clock signal by using a control circuit with a phase control block and a frequency control block to determine the edge position of the clock signal and generate a frequency selection signal, allowing the generation of a second clock signal at a higher frequency, thereby supporting higher data transmission rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock signal frequency is increased to support higher data transmission rates, then the data transmission rate is improved, but the circuit board frequency limitation is exceeded causing signal integrity degradation
Solution Approach 1:
The patent divides the clock signal processing into two separate domains: a first clock domain with frequency F1 that operates within circuit board limits, and a second clock domain with frequency F2 (higher than F1) that operates internally. The phase-locked loop circuit segments the frequency multiplication function from the data transmission function, allowing high-speed internal operation while maintaining compatibility with lower-speed external interfaces.
Solution Approach 2:
The phase-locked loop circuit acts as an intermediary device that receives the low-frequency clock signal from the circuit board and generates a high-frequency clock signal for internal operations. This mediator enables the system to bridge the gap between the limited external clock frequency and the required internal clock frequency for high-speed data transmission.
2Productivity
If a phase-locked loop circuit is introduced to generate higher frequency clock signals, then data transmission rates are improved, but the device complexity increases
Solution Approach 1:
The phase-locked loop circuit performs multiple functions simultaneously: it acts as a frequency multiplier to generate the second clock signal, serves as a phase synchronizer to maintain alignment between clock domains, and functions as a signal conditioner for reliable latching. This multi-functionality reduces the need for separate circuits and minimizes overall system complexity.
Solution Approach 2:
The invention changes the frequency parameter of the clock signal through the phase-locked loop, transforming a low-frequency input clock into a high-frequency output clock. By adjusting the frequency parameter dynamically, the system can adapt to different data transmission rate requirements without redesigning the entire circuit architecture.
Data Source
AI summary
A control circuit receives a first clock signal at a first frequency, a frequency division signal specifying a divisor number, and a second clock signal at a second frequency (higher than the first frequency). The control circuit includes a phase control block that defines non-overlapping portions of a pulse of the second clock to include center, left and right portions. A determination is then made as to whether an edge of the first clock is located within the center portion. In response to such a determination, a number of periods of the second clock signal which occur within one or more periods of the first clock signal is compared to a number derived from the divisor number to generate a frequency selection signal indicative of that comparison. A controlled oscillator circuit generates the second clock signal at the second frequency, wherein the second frequency is specified by the frequency selection signal. To the extent the edge of the first clock is located within either the left or right portions, phase adjustment is made to move the edge towards the center portion.