Clock Retiming Circuit Retention Mode for Fast Clock Recovery
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Solution Overview
Problem
Clock retiming circuits in electronic systems face challenges in maintaining operation and data transfer efficiency when the input clock is unavailable, as existing solutions do not efficiently transition between normal and low-power modes, leading to potential data transfer delays and increased power consumption.
Innovation Solution
A clock retiming circuit with a self-clock generation circuit, frequency multiplying circuit, and mode and calibration circuit that generates a retimed clock based on the input clock frequency, enters a low-power retention mode when the input clock is absent, and quickly re-establishes the clock upon its return, using stored calibration values to ensure fast locking and minimize power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock retiming circuit operates in normal mode continuously, then data transfer efficiency is maintained, but power consumption increases
Solution Approach 1:
The circuit dynamically switches between normal mode and retention mode based on the presence of the input clock signal. The mode and calibration circuit detects clock absence and transitions the frequency multiplying circuit to retention mode, enabling adaptive power management while maintaining data transfer efficiency when needed
Solution Approach 2:
The circuit changes its operational parameters by switching between different modes (normal and retention). In retention mode, the frequency multiplying circuit adjusts its parameters to maintain minimal operation with reduced power consumption, while calibration values are preserved for quick re-establishment
2Use of energy by moving object
If the clock retiming circuit enters retention mode during input clock absence, then power consumption is reduced, but data transfer delays may occur
Solution Approach 1:
The circuit performs preliminary calibration during normal operation and stores calibration values in calibration storage. When transitioning to retention mode and back, these pre-stored calibration values enable fast locking and quick re-establishment of the retimed clock, minimizing data transfer delays
Solution Approach 2:
The circuit rushes through the clock re-establishment process by using stored calibration values to quickly re-lock the frequency multiplying circuit when the input clock returns, significantly reducing the time needed to restore normal data transfer operation
3Stability of the object's composition
If the frequency multiplying circuit continuously locks to the reference clock, then retimed clock stability is maintained, but power consumption increases during clock absence
Solution Approach 1:
The circuit implements periodic calibration during retention mode instead of continuous operation. The mode and calibration circuit periodically re-calibrates the frequency multiplying circuit using stored calibration values, maintaining sufficient stability while consuming minimal power during input clock absence
Data Source
AI summary
A clock retiming circuit and method of operating a clock retiming circuit are described herein. A clock retiming circuit generates a retimed clock based on an input clock. The clock retiming circuit may have a normal mode when the input clock is available to the clock retiming circuit, and a retention mode that is entered in response to the input clock no longer being present. The clock retiming circuit resumes the normal mode in response to the clock again being present. The retention mode is a low current mode, in one aspect. Thus, the clock retiming circuit may operate in a low current mode when the input clock is not available. The clock retiming circuit may be tolerant to loss of the input clock. The clock retiming circuit may quickly re-establish the retimed clock in response to the input clock again becoming available.