Clock Routing for Non-Pipelined Execution Units
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Solution Overview
Problem
Modern GPUs with programmable shaders consume significant power due to active clock signals, which is problematic in mobile graphics applications where power is limited, and pipelined processors rely on clock signals for data transfer, leading to increased power consumption.
Innovation Solution
The implementation of non-pipelined execution units that do not use or receive clock signals, with clock lines routed only throughout the apparatus and not into execution units, reducing the length of clock lines and power consumption, and the use of a split datapath for efficient clock gating in clocked front-end circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock lines are routed throughout the entire processor including execution units, then data transfer between pipeline stages can be timed accurately, but power consumption increases due to longer clock lines
Solution Approach 1:
The processor is divided into pipelined front-end circuitry and non-pipelined execution units. Clock lines are routed only to the front-end circuitry, segmenting the clock distribution network to reduce its length and power consumption while maintaining timing for data transfer in the pipelined portion.
Solution Approach 2:
Different parts of the processor have different clocking characteristics: the front-end circuitry receives clock signals for timed data transfer, while execution units operate without clock signals. This local differentiation optimizes power consumption by eliminating unnecessary clock distribution to execution units.
2Productivity
If pipelined architecture is used for data transfer, then processing throughput increases, but power consumption increases due to active clock signals throughout the pipeline
Solution Approach 1:
The processor architecture is segmented into pipelined front-end circuitry that handles instruction fetch, decode, and dispatch with clock timing, and non-pipelined execution units that perform computations without clock signals. This segmentation maintains high throughput in the front-end while reducing power consumption in the execution portion.
Solution Approach 2:
Clock signals are applied periodically only to the front-end circuitry where timing is critical for pipeline operation, while execution units operate asynchronously without periodic clocking, reducing overall power consumption while maintaining processing throughput.
Data Source
AI summary
Techniques are disclosed relating to clock routing techniques in processors with both pipelined and non-pipelined circuitry. In some embodiments, an apparatus includes execution units that are non-pipelined and configured to perform instructions without receiving a clock signal. In these embodiments, one or more clock lines routed throughout the apparatus do not extend into the one or more execution units in each pipeline, reducing the length of the clock lines. In some embodiments, the apparatus includes multiple such pipelines arranged in an array, with the execution units located on an outer portion of the array and clocked control circuitry located on an inner portion of the array. In some embodiments, clock lines do not extend into the outer portion of the array. In some embodiments, the array includes one or more rows of execution units. These arrangements may further reduce the length of clock lines.