Clock Signal Routing Partitioning for IC Congestion
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Solution Overview
Problem
Existing methods for routing clock signals in programmable integrated circuits often result in congested regions, leading to reduced clock utilization and inability to route signals effectively, as they limit the potential solution space and disrupt initial placements when trying to address congestion.
Innovation Solution
The method involves determining initial partitions of clock sources and loads, identifying congested regions, and redefining partitions by excluding the clock source, allowing for alternative routing options and minimizing the movement of clock loads to avoid congested areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock sources and clock loads are placed in the same partition, then routing resources are allocated efficiently, but congested clock regions are created leading to routing failures
Solution Approach 1:
The patent divides the IC into multiple partitions, each containing a clock source and its associated clock loads. This segmentation allows independent routing of clock signals within each partition, preventing global congestion and enabling localized routing solutions that improve overall routing success rate.
Solution Approach 2:
The patent extracts clock sources from their respective partitions to create separate clock load partitions. By removing clock sources from the partition containing clock loads, the method eliminates the congestion caused by having both elements in the same partition, thereby enabling successful routing.
2Adaptability or versatility
If partitions are redefined to exclude clock sources, then routing flexibility is improved, but partition complexity increases
Solution Approach 1:
The patent segments the original partitions into two distinct types: clock source partitions (containing only clock sources) and clock load partitions (containing only clock loads). This segmentation simplifies the overall partition structure by creating clear, non-overlapping regions that are easier to manage and route.
Solution Approach 2:
The patent extracts clock sources from the mixed partitions and creates separate dedicated partitions for them. This extraction, while initially increasing partition count, actually simplifies the routing process by eliminating the need to navigate through congested mixed regions, thereby improving routing flexibility without proportionally increasing complexity.
Data Source
AI summary
Approaches for routing clock signals of a circuit design on an IC include determining initial partitions of clock sources and clock loads. Each initial partition includes one of the clock sources and a subset of the clock loads associated with the one clock source, and initial each partition defines an area of the IC in which the one of the clock sources and the associated subset of clock loads are placed. A processor determines for each of the initial partitions, whether or not the initial partition has a congested clock region. For each initial partition determined to have a congested clock region, the processor defines a respective new partition by excluding the one of the clock sources from the new partition. The new partition includes the subset of the clock loads and does not include the one clock source. The processor then routes clock signals from the clock sources to the clock loads.