Multi-Point Clock Sampling for High-Speed Data Synchronization

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Solution Overview

Problem

High-speed data communication systems face reliability issues due to timing misalignment between data signals and clock signals, which degrades data recovery, especially as data rates increase, as existing synchronization methods fail to account for uncertainties in data symbol widths.

Innovation Solution

A receiver and transmitter system that uses a delay line and circuitry to produce multiple sampling signals to track both phase and width parameters of data symbols, adjusting sampling instances to align with data symbol centers, thereby improving synchronization accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single sampling clock signal is used for data recovery, then the device complexity is reduced, but the synchronization accuracy between data and clock signals deteriorates at high data rates

Engineering Contradiction:
Improvesampling circuit complexityVSAvoiddata sampling accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent segments the single sampling clock signal into multiple sampling signals (early, middle, late) that sample data at different time positions within the symbol period. This segmentation allows the system to track both phase and width parameters separately, improving synchronization accuracy without requiring a completely complex redesign of the sampling circuit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds a time dimension to the sampling process by introducing multiple sampling instances (early, middle, late) instead of a single sampling point. This dimensional expansion enables the system to capture both phase alignment and symbol width information, resolving the accuracy-complexity contradiction.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If phase tracking only is implemented, then the device complexity is reduced, but the data recovery reliability deteriorates due to unaccounted symbol width variations

Engineering Contradiction:
Improvesynchronization circuit complexityVSAvoiddata recovery reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent segments the synchronization function into two independent tracking loops: phase tracking and width tracking. The early and late sampling signals are used to extract width information, while the middle sampling signal handles phase alignment. This segmentation allows reliable data recovery by accounting for both phase and width variations without excessive complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic tracking of both phase and width parameters using feedback loops that continuously adjust the sampling timing based on detected errors. This dynamic adaptation to varying symbol widths and phase shifts improves data recovery reliability in changing channel conditions.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If multiple sampling signals with separate delay control are used, then the synchronization accuracy is improved, but the device complexity increases

Engineering Contradiction:
Improvesampling timing precisionVSAvoiddelay line control complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies different delay control strategies to different sampling signals: the middle sampling signal uses phase-based delay control for precise center alignment, while the early and late sampling signals use width-based delay control relative to the middle signal. This local differentiation of control quality achieves high precision without uniformly increasing complexity across all sampling paths.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11962310B1Synchronization between data and clock signals in high-speed interfaces
Publication Date: 2024.04.16 APPLE INC
  • US11962310B1 patent drawing
  • US11962310B1 patent drawing
  • US11962310B1 patent drawing

AI summary

A receiver includes an interface, a delay line and circuitry. The interface receives data symbols and a clock signal for strobing the data symbols at selected positions. The delay line produces from the clock signal a middle sampling signal, and early and late sampling signals that respectively precedes and succeeds the middle sampling signal. The circuitry samples the data symbols using the middle, early and late sampling signals to produce early and late error signals. Based on the early and late error signals the delay line delays the middle, early and late sampling signals by separate delay values, so as to track both (i) a phase parameter indicative of a deviation between the middle sampling signal and the selected positions of the data symbols, and (ii) a width parameter indicative of a time duration of the data symbols, and to output the data symbols strobed using the middle sampling signal.