Clock Frequency Scaling with Glitchless PLL Switching
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Solution Overview
Problem
Existing clock management systems in electronic devices face challenges with frequency scaling, as changes in clock frequency can lead to undesired behavior, downtime, and excessive power consumption due to large current variations during transitions, especially when reconfiguring oscillating circuitry like phase-locked loops.
Innovation Solution
The implementation of circuitry and methods that enable smooth, glitchless transitions between clock frequencies using gate circuitry, latch-based memories, and control circuitry to sense environmental and power conditions, allowing incremental frequency changes and storing multiple configurations for oscillating circuitry, thereby reducing current consumption and stabilizing clock signals quickly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamic reconfiguration of oscillating circuitry is employed to change clock frequency, then frequency flexibility is improved, but downtime occurs until the circuit stabilizes and excessive power is consumed during transitions
Solution Approach 1:
The system pre-configures multiple oscillating circuitries (PLLs) with different frequency settings before operation. When frequency scaling is needed, the system simply switches between pre-configured circuitries rather than reconfiguring in real-time, eliminating transition downtime and reducing power consumption during frequency changes.
Solution Approach 2:
A clock control unit acts as an intermediary that manages multiple PLLs and selects appropriate clock sources based on environmental conditions and power requirements. This mediator coordinates the switching between different frequency configurations, ensuring smooth transitions without excessive power consumption or stabilization downtime.
2Adaptability or versatility
If large increments in clock frequency are used for scaling, then frequency adjustment range is improved, but very large currents are drawn consuming excessive power
Solution Approach 1:
The frequency scaling process is segmented into multiple incremental steps rather than a single large jump. The clock control unit switches through intermediate frequency configurations, allowing the system to achieve large frequency adjustments while keeping current consumption at manageable levels during each transition step.
Solution Approach 2:
The system dynamically selects from multiple pre-configured PLLs with different frequency dividers and configurations. By having multiple oscillating circuitries ready with different frequency settings, the system can adjust frequency in controlled increments without drawing excessive current, as each PLL is designed to operate efficiently at its specific frequency range.
3Adaptability or versatility
If clock frequency is changed during operation, then power management flexibility is improved, but undesired behavior and instability occur
Solution Approach 1:
Multiple PLLs are pre-configured with specific frequency settings before operation begins. The clock control unit maintains a registry of available clock sources and their configurations, allowing it to select appropriate frequencies without disrupting system operation. This preliminary preparation ensures that frequency changes can occur during operation without causing instability or undesired behavior.
Solution Approach 2:
The clock control unit continuously monitors environmental conditions (temperature, power availability) and system state, using this feedback to select appropriate clock frequencies from the available PLLs. This feedback mechanism ensures that frequency changes are made only when appropriate, maintaining operational stability while providing power management flexibility.
Data Source
AI summary
Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed.