Clock Distribution Circuit Scaling for Low Phase Noise
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed clock distribution systems face challenges in achieving low-noise output due to high VCO gain, which amplifies control voltage noise, leading to increased phase noise and jitter in the output frequency.
Innovation Solution
A clock distribution circuit comprising a comparator, filter, scaling unit, and oscillator, where the scaling unit scales down the filtered error signal by a factor less than 1 to produce a control signal, reducing noise and phase noise in the output frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high VCO gain is used to cover the required frequency range in limited voltage range, then the frequency range coverage is improved, but the phase noise and jitter in output frequency increase due to amplified control voltage noise
Solution Approach 1:
The control voltage noise is segmented into two independent components: a deterministic component (from charge pump current) and a random component (from power-ground noise). By separating these noise sources, the patent applies different handling strategies - the deterministic component is compensated through calibration, while the random component is minimized through circuit design, thereby reducing overall phase noise while maintaining frequency range coverage
Solution Approach 2:
The patent changes the operating parameters of the VCO by dynamically adjusting its gain characteristic. Through calibration processes, the VCO gain is optimized to compensate for PVT variations, allowing the system to maintain accurate frequency output with reduced phase noise across the required frequency range without needing excessively high fixed gain
2Object-generated harmful factors
If multiple V-f curves are deployed to reduce phase noise by using low VCO gain, then the phase noise is reduced, but the circuit complexity and manufacturing cost increase
Solution Approach 1:
The system performs self-calibration to determine and store the optimal VCO gain and control voltage range for different process corners. This self-service approach eliminates the need for external calibration equipment and complex multi-V-f curve circuitry, reducing both circuit complexity and manufacturing cost while maintaining low phase noise performance
Solution Approach 2:
The patent implements preliminary calibration during manufacturing to characterize the VCO gain and control voltage range for each process corner. These calibration results are stored and used during normal operation, allowing the system to achieve low phase noise with a single V-f curve instead of multiple curves, thereby simplifying the circuit
Data Source
AI summary
A clock distribution circuit and a method thereof. The clock distribution circuit comprises a comparator, a filter, a scaling unit, and an oscillator. The comparator compares a reference signal and a feedback signal to generate an error signal. The filter is coupled to the comparator and outputs a filtered signal based on the error signal. The scaling unit is coupled to the comparator, and scales down the filtered signal by a scaling factor to form a control signal. The oscillator is coupled to the scaling unit, and produces the feedback signal based on the control signal. And the scaling factor is less than 1.