Clock Frequency Scaling with Glitchless PLL Switching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock frequency scaling methods in electronic devices, such as ASICs and PLDs, often result in undesired behavior, downtime, and excessive power consumption due to large current spikes during frequency changes, as they require reconfiguration of oscillating circuitry and may lead to glitches during transitions.
Innovation Solution
The implementation of circuitry and methods that allow for smooth, glitchless transitions between clock frequencies using gate circuitry, latch-based memories, and control circuitry that senses environmental and power conditions to manage incremental frequency changes, reducing current consumption and enabling quick convergence to new frequency settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamic reconfiguration of oscillating circuitry is used to change clock frequency, then frequency flexibility is improved, but downtime occurs until the circuit stabilizes and large currents are drawn during transition
Solution Approach 1:
The patent pre-configures multiple oscillating circuitries (PLLs) with different frequency settings before operation. When frequency scaling is needed, the system simply switches between pre-configured circuitries rather than reconfiguring in real-time, eliminating stabilization downtime. The desired frequency circuitry is already prepared and ready for immediate activation.
Solution Approach 2:
The patent introduces a clock control unit as an intermediary that manages the switching between multiple PLLs. This control unit coordinates the transition by gating the output of the current PLL and enabling the target PLL, ensuring smooth frequency transitions without direct reconfiguration of the oscillating circuitry itself, thereby avoiding stabilization delays.
2Adaptability or versatility
If large increments in clock frequency are used for scaling, then frequency adjustment range is improved, but excessive power is consumed due to very large currents during modification
Solution Approach 1:
The patent segments the frequency scaling process into multiple small incremental steps rather than making large jumps. Multiple PLLs are configured with intermediate frequency values, and the system transitions through these steps sequentially. This segmentation reduces the current spikes associated with large frequency changes while achieving the same overall frequency adjustment range.
Solution Approach 2:
The patent implements dynamic frequency scaling by enabling real-time switching between PLLs with incrementally different frequency settings. This dynamic approach allows the system to adjust frequency in controlled steps during operation, maintaining adaptability while managing power consumption through gradual transitions rather than abrupt changes.
3Adaptability or versatility
If reconfiguration of oscillating circuitry is performed to change frequency, then frequency scaling capability is improved, but glitches occur during the transition process
Solution Approach 1:
The patent prepares multiple PLLs with predetermined frequency configurations before operation. Since these circuitries are pre-configured and stable, switching between them eliminates the reconfiguration glitches that would occur if a single PLL had to be reprogrammed in real-time. The target frequency is already established in the selected PLL, ensuring glitchless transition.
Solution Approach 2:
The clock control unit acts as an intermediary that manages the switching process between PLLs. It uses gating signals to smoothly transition from one PLL output to another, ensuring that the frequency signal remains stable and free of glitches during the switch. This intermediary control prevents direct reconfiguration disturbances from affecting the output signal.
Data Source
AI summary
Systems and methods described herein are related to clock signal generation for synchronous electronic circuitry. Power management in electronic devices circuitry may be implemented by scaling the frequency multiple functional modules implemented in the synchronous electronic circuitry. The present disclosure discussed clock generators that may provide frequency scaling of clock signals for functional modules within an electronic device. Moreover, certain clock signal generators may reduce mitigate generation of large currents during frequency scaling by employing circuitry that leads to incremental frequency changes. Circuitry that allows substantially glitchless or reduced-glitch transition between clock rate frequencies are also discussed.