Digital Clock Scattering for CMOS Image Sensor Noise Reduction

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Solution Overview

Problem

Conventional image sensors using CMOS technology are prone to pixel noise due to power fluctuations, which affect the quality of captured images.

Innovation Solution

The implementation of an imaging device with a digital processing circuitry that includes a digital clock generator capable of scattering the digital clock in response to image sensing operations, reducing digital power consumption and minimizing the influence of power fluctuations through clock gating or division during analog-to-digital conversion periods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If digital processing circuitry operates continuously with constant clock signaling, then processing speed and productivity are maintained, but power fluctuations occur causing pixel noise

Engineering Contradiction:
Improveimage qualityVSAvoidpixel noise
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies periodic action by scattering the digital clock signal during analog-to-digital conversion periods. The clock generator selectively disables or reduces clock signaling during specific time windows when ADC operations are performed, creating a periodic on-off pattern that prevents continuous power fluctuations from affecting pixel noise while maintaining processing capability during non-conversion periods.

Inventive Principle:
Principle #19Periodic action

2Reliability

If clock scattering is implemented during analog-to-digital conversion, then pixel noise is reduced, but processing continuity is interrupted

Engineering Contradiction:
Improveimage qualityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent implements partial action by applying clock scattering only during specific ADC conversion periods rather than continuously. The digital processing circuitry maintains full clock operation during non-conversion periods, partially disabling the clock only when necessary for ADC operations. This selective approach reduces pixel noise during critical conversion windows while preserving processing speed during other time periods.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11601612B2Imaging device and method of operating the same
Publication Date: 2023.03.07 SAMSUNG ELECTRONICS CO LTD
  • US11601612B2 patent drawing
  • US11601612B2 patent drawing
  • US11601612B2 patent drawing

AI summary

An imaging device includes an image sensing circuitry configured to receive image signals from pixels, to convert the received image signals into image data, and to output the image data. The imaging device includes a digital processing circuitry configured to process image data in synchronization with a digital clock. The digital processing circuitry includes a digital clock generator configured to generate the digital clock. The digital clock generator is configured to scatter the digital clock, in response to the image sensing circuitry converting the image signals into the image data.