Clock Scheduling Optimization in EDA Tools
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Solution Overview
Problem
In deep sub-micron VLSI, traditional clock skew analysis in EDA tools primarily focuses on critical design timing, neglecting area and power optimization, making it challenging to efficiently synchronize clock signals across complex ICs without significant area and power costs.
Innovation Solution
A method and system for optimizing clock scheduling in EDA tools by determining optimal clock anchor points and scheduling clock skews based on slack statistics, which allows for refined timing and area optimization without impacting power, using a computer-implemented system to generate clock scheduling constraints for clock tree synthesis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional clock skew analysis is used to focus on critical design timing, then timing performance is improved, but area and power optimization are neglected
Solution Approach 1:
The patent changes the parameters of clock skew scheduling by introducing slack-based skew values instead of traditional zero-skew or fixed skew approaches. By dynamically adjusting clock skew parameters based on slack statistics from timing analysis, the method achieves both timing closure and area optimization. The clock skew for each anchor point is calculated as a function of slack values, allowing flexible parameter tuning to resolve the contradiction between timing precision and area efficiency.
2Manufacturing precision
If traditional clock skew analysis is used to focus on critical design timing, then timing performance is improved, but power consumption increases
Solution Approach 1:
The patent modifies the clock skew parameters dynamically based on slack statistics, enabling power optimization alongside timing performance. By calculating clock skews as functions of slack values rather than using fixed or uniform skew values, the method reduces unnecessary clock distribution activity and optimizes power consumption in the clock network while maintaining timing requirements.
3Manufacturing precision
If clock skew is optimized for timing closure, then timing performance is improved, but area reduction is limited
Solution Approach 1:
The patent introduces slack-based clock skew parameter optimization that simultaneously addresses timing closure and area reduction. By computing clock skew values as functions of slack statistics from timing analysis, the method enables EDA tools to optimize both timing and area parameters together, rather than treating them as separate optimization problems. This parameter-based approach allows the clock tree synthesis to achieve timing closure while minimizing the area occupied by clock distribution logic.
Data Source
AI summary
A method and computer-implemented system for use with an electronic design automation (EDA) tool to optimize clock scheduling. Based on an initial timing and area optimized design for a logic circuit, an optimal set of clock anchor points on a clock tree for the logic circuit, and slack statistics for a plurality of elements in the logic circuit, are determined. Clock skews for the CAPs associated with the plurality of elements are then scheduled as a function of the slack statistics. A refined timing and area optimized design for the logic circuit is generated based on the clock skews, and the refined timing and area optimized design is utilized as input to a clock tree synthesis module of the EDA tool.