Clock Scheme Circuit With Local Frequency Multiplication
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Solution Overview
Problem
Mobile DDR memory's high-speed clock scheme circuits consume excessive power, necessitating a low-power design for efficient operation in mobile electronic devices.
Innovation Solution
A clock scheme circuit with a global clock generator and a local clock generator using a frequency multiplier, such as a multiplying delay-locked loop (MDLL), delay-locked loop (DLL), or phase-looked loop (PLL), to generate a high-frequency local clock signal from a low-frequency global clock signal, reducing power consumption along the global clock trace.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed clock scheme circuit is used in mobile DDR memory, then the data transmission speed is improved, but the power consumption increases
Solution Approach 1:
The clock scheme circuit is divided into two independent parts: a global clock generator that produces a low-frequency global clock signal, and a local clock generator at each memory bank that multiplies this signal to produce the high-frequency local clock signals needed for fast data transmission. This segmentation allows the high-speed operation to be localized only where needed, rather than requiring the entire system to operate at high speed and consume high power.
Solution Approach 2:
The patent applies different clock frequencies to different parts of the system: a low-frequency global clock signal is distributed throughout the system, while high-frequency local clock signals are generated only at the memory banks where high-speed data transmission is required. This local quality approach ensures that high power consumption is confined to small localized areas rather than the entire system.
2Speed
If a high-frequency clock signal is distributed throughout the system, then the data transmission speed is improved, but the power consumption along the clock traces increases
Solution Approach 1:
The clock distribution system is segmented into a global clock network carrying low-frequency signals and local clock networks at each bank carrying high-frequency signals. The global clock traces only need to handle low-frequency signals, reducing their power consumption, while the high-frequency traces are limited to short local connections at each memory bank.
Solution Approach 2:
The global clock signal acts as an intermediary that carries timing information at low frequency across the entire system. Each local clock generator then uses this low-frequency global clock as a reference to generate the high-frequency local clock signals needed for fast data transmission, eliminating the need to distribute high-frequency signals throughout the entire system.
Data Source
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AI summary
A clock scheme circuit with low power consumption is shown. A local clock generator is coupled to a global clock generator through a global clock trace to receive a global clock signal, and generate a local clock signal based on the global clock signal. The local clock generator uses a frequency multiplier to multiply the frequency of the global clock signal by a multiplication factor of not less than 1. Thus, the global clock signal transferred through the global clock trace can be a lower-frequency signal in comparison with the local clock signal. The power consumption along the global clock trace is considerably reduced.