Memory Interface Clock Segmentation for Multi-Memory Data Throughput
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Solution Overview
Problem
The increasing data throughput in computing systems often exceeds the data bandwidth or communication speed of interfaces connected to non-volatile memory devices, leading to data bottlenecks that degrade the performance of computing systems.
Innovation Solution
A memory system with an interface circuit that divides a received clock signal into multiple clock signals based on the number of non-volatile memories, allowing for adaptive operating frequency adjustment to synchronize data exchange between the memory controller and non-volatile memories, thereby reducing loading and enhancing data throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data throughput is increased to meet computing system demands, then data bandwidth requirement increases, but interface communication speed becomes insufficient causing data bottlenecks
Solution Approach 1:
The interface circuit is divided into multiple parallel lanes (first interface circuit, second interface circuit, etc.) that can simultaneously transmit data. Each lane operates at a lower individual speed but collectively they provide aggregated bandwidth that meets the high throughput requirements, resolving the contradiction between individual interface speed limits and overall data throughput needs.
Solution Approach 2:
Multiple interface circuits are merged into a unified data transmission system where data from multiple non-volatile memories is combined and transmitted through parallel paths. The memory controller aggregates data from multiple memories via multiple interface circuits, effectively combining their individual bandwidths to achieve the required overall data throughput.
2Quantity of substance
If multiple non-volatile memories are connected to increase storage capacity, then data bandwidth potential increases, but clock signal synchronization becomes complex
Solution Approach 1:
The clock signal distribution is segmented into multiple independent paths, with each interface circuit receiving its own divided clock signal from the memory controller. This segmentation allows each memory device to be independently clocked without requiring complex inter-memory synchronization, simplifying the overall system while supporting multiple memories.
Solution Approach 2:
The memory controller acts as an intermediary that generates and distributes divided clock signals to multiple interface circuits and non-volatile memories. This intermediary approach centralizes clock management, allowing the controller to handle synchronization logic while individual memories operate independently based on received clock signals.
3Productivity
If interface circuit operates at maximum frequency to improve data exchange speed, then productivity increases, but stability may be compromised
Solution Approach 1:
The interface circuit dynamically adjusts its operating frequency based on the specific data transmission task and memory device characteristics. The system can operate at maximum frequency when conditions permit for high-speed transfer, and reduce frequency when stability is prioritized, providing adaptive performance that balances speed and reliability requirements.
Solution Approach 2:
The system changes operational parameters including clock frequency and data width to optimize performance. By adjusting these parameters based on workload requirements and memory device capabilities, the interface circuit can achieve maximum throughput when needed while maintaining stable operation under varying conditions, effectively managing the trade-off between speed and reliability.
Data Source
AI summary
A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.