Glitch-Free Clock Selection Circuit for ATPG and LBIST Testing
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Solution Overview
Problem
Integrated circuits face glitches during switching between functional and test clocks in ATPG and LBIST modes, necessitating circuitry that can generate test clocks without glitches.
Innovation Solution
A test circuit with a clock selection circuit that includes clock logic, a multiplexing circuit, and a clock gate circuit, capable of generating ATPG and LBIST clocks, ensuring glitch-free switching between functional and test clocks by using mode signals to control clock generation and multiplexing between ATPG and functional clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the integrated circuit switches from functional clock to test clock during test mode, then test operations (ATPG/LBIST) can be performed, but glitches occur during the switching process
Solution Approach 1:
The circuit prepares test clocks in advance using dedicated clock generation circuits (CGC) that are activated before test operations begin. The clock selection circuit is pre-configured with multiple clock inputs including functional clock and multiple test clocks, allowing seamless transition without glitches during mode switching.
Solution Approach 2:
A clock selection circuit acts as an intermediary between the functional clock and test clocks. This circuit receives mode selection signals and automatically switches between different clock sources, isolating the glitch-prone switching from the actual test operations and ensuring stable clock delivery during mode transitions.
2Adaptability or versatility
If separate test clocks are used for ATPG and LBIST modes, then each test mode can have optimized clock characteristics, but circuit complexity increases for clock generation and switching
Solution Approach 1:
The clock selection circuit is designed with universal functionality to handle multiple clock sources (functional clock, ATPG test clock, LBIST test clock) and automatically select the appropriate clock based on the operating mode. This multi-functional approach consolidates what would otherwise require separate dedicated switching circuits for each test mode.
Solution Approach 2:
The clock generation and selection system is made dynamic through mode selection signals that automatically configure the clock selection circuit for the current test mode. The circuit adapts its behavior based on whether ATPG or LBIST mode is active, providing mode-optimized clock characteristics without requiring manual reconfiguration or fixed dedicated circuits for each mode.
Data Source
AI summary
A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.