Data Output Clock Selection Circuit Eliminates Glitches
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Solution Overview
Problem
Conventional data output clock selection circuits are frequency-limited due to the requirement for a specific delay range in delay chains, which varies with voltage, temperature, and process variations, leading to potential glitches and limited operational frequency range.
Innovation Solution
A data output clock selection circuit that uses a combinational logic circuit and sequential logic circuits, where a reset control signal is generated based on the output clock signals, asynchronously resetting the sequential logic circuits to select between input and output clock signal pairs, eliminating glitches and frequency limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a delay chain is used to filter clock signals, then pulse filtering capability is improved, but the circuit becomes frequency-limited and requires large layout area
Solution Approach 1:
The patent extracts the delay chain component from the clock selection circuit and replaces it with a pulse filter that directly monitors the C and C# signals. This removes the frequency-limiting delay element while maintaining the ability to filter erroneous wide pulses, thereby resolving the contradiction between pulse filtering capability and operational frequency range.
Solution Approach 2:
The patent replaces the mechanical delay-based filtering approach with an electronic logic-based pulse filter. Instead of relying on time-delayed signal comparison, the new circuit uses logical AND operations on the clock signals themselves to detect and filter erroneous pulses, enabling operation across a wider frequency range without the layout area penalty of delay chains.
2Reliability
If a delay chain is used to ensure proper clock signal filtering, then pulse separation filtering is improved, but power consumption and layout area increase
Solution Approach 1:
The patent replaces the power-hungry delay chain with a simpler, lower-power logic circuit implementation. The new pulse filter uses basic logic gates (AND, NOT) that consume significantly less power than the delay chain while achieving the same pulse separation filtering function, thus resolving the contradiction between reliable pulse filtering and power consumption.
3Reliability
If delay chain parameters are adjusted for voltage and temperature variations, then filtering reliability is improved, but device complexity increases
Solution Approach 1:
The patent creates a universal pulse filter circuit that operates reliably across voltage and temperature variations without requiring parameter adjustments. The logic-based design inherently adapts to environmental conditions, eliminating the need for complex delay chain parameter tuning while maintaining filtering reliability, thus resolving the contradiction between reliable filtering and device complexity.
Data Source
AI summary
A method for selecting a data output clock signal includes providing a complementary output clock signal pair to a combinational logic circuit, thereby generating a reset control signal. The reset control signal is activated if the complementary output clock signals have different values, and deactivated if these clock signals have the same predetermined value. The activated reset control signal asynchronously resets a pair of series connected flip-flops. The deactivated reset control signal enables the flip-flops to synchronously propagate a fixed logic signal in response to a clock signal of a complementary input clock signal pair. The output signal of the series-connected flip-flops is used to select the data output clock signal from the first complementary clock signal pair and the second complementary clock signal pair.