Clock Selection Circuit for Hierarchical Distribution Networks
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Solution Overview
Problem
In distributed computing environments, synchronizing time across multiple devices is challenging due to independent notions of time, leading to difficulties in determining the priority of conflicting requests and requiring complex synchronization techniques that are often inaccurate or time-consuming.
Innovation Solution
A clock selection circuit, potentially an Integrated Circuit (IC) like a Field Programmable Gate Array (FPGA), analyzes and validates clock signals by comparing timestamps, assigns priority, and seamlessly switches between multiple clock sources in a hierarchical distribution network to ensure accurate and synchronized timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Network Time Protocol (NTP) is used to synchronize time between networked computers, then time synchronization is achieved, but accuracy is insufficient and complexity increases
Solution Approach 1:
The patent extracts the time synchronization function from the data network and implements it through a separate, dedicated clock distribution network. This dedicated network carries only clock signals, eliminating the complexity and inaccuracies of using NTP over general-purpose data networks while providing precise time synchronization.
Solution Approach 2:
The patent introduces a dedicated clock distribution network as an intermediary between time sources and computing devices. This intermediary specialized network provides accurate time synchronization without the complexity of NTP, acting as a mediator that separates the time synchronization function from data communication.
2Reliability
If a backup system clock is used for failover, then system reliability is improved, but re-synchronization time increases
Solution Approach 1:
The patent maintains multiple clock sources in the dedicated clock distribution network that are already synchronized and ready. When failover is needed, the system can immediately switch to a pre-synchronized backup clock source without requiring time-consuming re-synchronization, thus maintaining high reliability with minimal time loss.
3Measurement precision
If multiple clock sources are distributed in a hierarchical network, then synchronization accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the clock distribution system into a hierarchical structure with multiple levels, where each level distributes clock signals to specific subsets of devices. This segmentation provides accurate synchronization within each segment while keeping the complexity of individual distribution units manageable and modular.
Data Source
AI summary
A clock selection circuit allows seamless switching between different clock signals in a clock distribution network. The clock selection circuit can be an Integrated Circuit (IC). The clock signals can be analyzed by a processor in communication with the IC to ensure the clock signals are validated. Analysis can include comparing time stamps between received pulses of the clock signals to determine if the clock signals are occurring at regular intervals. The processor can then assign a priority order to the clock signals and select one of the clock signals to use. An identifier associated with the selected clock signal can be programmed into the IC. The IC can then redistribute the selected clock signal to multiple other ICs in a hierarchical clock distribution network. Ultimately, the distributed clock signal can be received by server computers to ensure instances being executed have accurate and synchronized timing.