Clock Selection Unit Pipeline Reconfiguration for Image Processing
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Solution Overview
Problem
In image processing devices, the varying processing amounts across different calculation units in a pipeline lead to idle times due to mismatched clock signals, resulting in inefficient processing and increased power consumption.
Innovation Solution
The introduction of a clock selection unit and data delivery unit that adjust clock signals and data delivery timing between calculation units based on operation modes, allowing for flexible reconfiguration of the pipeline to match processing demands, thereby optimizing clock signal frequencies and reducing idle times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a pipeline with multiple calculation units is used to perform various image processing operations, then processing versatility and functionality are improved, but idle times occur due to mismatched processing speeds between different calculation units
Solution Approach 1:
The patent applies dynamics by making the pipeline configuration changeable according to operation modes. The control unit dynamically reconfigures which calculation units are included in the pipeline and their arrangement order based on the specific image processing task being performed. This allows the system to adapt the pipeline structure to match the processing requirements of different operation modes, thereby reducing idle times caused by mismatched processing speeds while maintaining versatility across multiple processing types.
2Productivity
If calculation units operate with different clock signal frequencies to match their processing amounts, then processing efficiency is improved, but device complexity increases due to multiple clock signals
Solution Approach 1:
The patent applies local quality by assigning different clock signal frequencies to different calculation units based on their specific processing requirements. Each calculation unit receives a clock signal frequency that matches its processing amount and speed characteristics. This localized optimization allows each unit to operate at peak efficiency without forcing the entire system to run at a uniform speed, thereby improving overall processing efficiency while managing complexity through targeted frequency assignment.
Solution Approach 2:
The patent applies parameter changes by varying the clock signal frequency parameter for different calculation units. The control unit selects and supplies appropriate clock signal frequencies from multiple available frequencies to each calculation unit based on the operation mode and processing requirements. This parameter adjustment allows the system to optimize processing efficiency for each unit while the control unit manages the complexity of coordinating multiple frequencies.
3Device complexity
If the pipeline configuration is fixed, then device complexity is reduced, but processing efficiency decreases due to inability to optimize for different operation modes
Solution Approach 1:
The patent applies dynamics by implementing a reconfigurable pipeline where the control unit can dynamically change which calculation units are included in the pipeline and their arrangement order based on the operation mode. This dynamic reconfiguration allows the system to optimize the pipeline for specific processing tasks such as contraction, expansion, or other image processing operations, thereby improving processing efficiency without requiring a completely fixed or permanently complex structure.
Solution Approach 2:
The patent applies universality by designing a pipeline architecture that can serve multiple processing functions through reconfiguration. The same set of calculation units can be arranged in different configurations to handle various operation modes and processing types. This multi-functionality allows the system to maintain relatively simple hardware while achieving high processing efficiency across different tasks by dynamically adapting the pipeline configuration to match the specific processing requirements.
Data Source
AI summary
An image processing device includes a plurality of clock selection units configured to select a clock signal to be supplied to each of a plurality of calculation units forming a pipeline from a plurality of clock signals and output the clock signal to the calculation unit, a data delivery unit disposed on the pipeline between the calculation unit to which a first clock signal is input and the calculation unit to which a second clock signal is input, and a control unit configured to control a selection of the clock signal and a combination and a disposition order of the data delivery unit and the calculation units forming the pipeline in accordance with an operation mode of image processing.