Glitch-Free Clock Selection Circuit for Sleep Mode Transitions
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Solution Overview
Problem
Existing wireless communications systems face inefficiencies in power consumption and latency due to the need to maintain network connections and handle requests during sleep mode transitions, particularly in battery-powered devices, where the wake-up process from low power modes results in increased power consumption and reduced throughput.
Innovation Solution
A clock selection circuit that seamlessly transitions between different clock sources, using a state machine and doublet registers to manage the switching between host and network clocks, ensuring glitch-free switching and efficient power management by maintaining low power states until necessary, allowing immediate handling of requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the system uses a low frequency sleep clock to reduce power consumption during sleep mode, then power consumption is reduced, but the system cannot handle incoming requests or maintain network connections without waking up periodically
Solution Approach 1:
The system performs preliminary actions by queuing incoming requests during sleep mode and preparing the wake-up sequence in advance. The host interface queues requests from the applications processor before the system wakes up, and the power sequencer prepares the wake-up sequence using the sleep clock, so that when the system wakes up, it can immediately handle requests without additional latency.
Solution Approach 2:
The patent introduces intermediary components to bridge the gap between sleep mode and active mode operations. The power sequencer acts as an intermediary that uses the sleep clock to manage wake-up timing and coordinate the transition to active clocks. The host interface serves as an intermediary that queues requests and manages the interface between the applications processor and the communications processor during sleep transitions.
2Reliability
If the system wakes up periodically to maintain network connections and handle requests, then network connectivity is maintained, but power consumption increases and throughput is reduced
Solution Approach 1:
The system implements periodic action through controlled wake-up intervals rather than continuous operation. The power sequencer uses the sleep clock to generate periodic wake-up signals that maintain network connections only when necessary. This allows the system to stay in low-power sleep mode between wake-up periods while still maintaining network connectivity, reducing overall power consumption compared to continuous operation.
Solution Approach 2:
The system provides self-service by automatically managing wake-up timing and request handling without external intervention. The power sequencer autonomously determines when wake-up is necessary based on queued requests and network requirements, and automatically coordinates the clock switching and power management sequences, reducing the need for external power management control.
3Use of energy by moving object
If the system switches between clock sources during sleep mode transitions, then power management is improved, but clock switching glitches can occur causing system instability
Solution Approach 1:
The system applies beforehand cushioning by using doublet registers to anticipate and prevent clock switching glitches. The doublet registers are designed to handle the clock transition before it occurs, providing a buffer that prevents glitches from propagating through the system. This cushioning mechanism ensures stable clock switching during power mode transitions without compromising system reliability.
Solution Approach 2:
The patent replaces traditional mechanical or simple electronic clock switching mechanisms with a more sophisticated doublet register-based switching system. The doublet registers use sequential logic to manage clock source transitions, substituting simple clock multiplexing with a controlled state-machine approach that eliminates glitches while maintaining power management efficiency.
4Device complexity
If the system uses a simple clock multiplexer for switching between clock sources, then device complexity is reduced, but glitch-free switching between different frequency clocks cannot be achieved
Solution Approach 1:
The system implements dynamic clock switching control through state machines that adapt the clock switching behavior based on the current power mode and request queue status. The clock selection is not static but dynamically adjusted based on system conditions, allowing glitch-free switching between different frequency clocks while managing complexity through conditional logic rather than complex circuitry.
Solution Approach 2:
The patent changes the parameters of clock switching by using doublet registers that are configured differently based on the source and destination clock frequencies. The switching mechanism adapts its behavior based on frequency parameters, enabling glitch-free transitions between clocks of different frequencies without requiring a single complex fixed circuit design.
Data Source
AI summary
A clock selector operative on two clocks operating on different domains and responsive to a SELECT input provides a transition from a first clock to a second clock, and from a second clock to a first clock with a dead zone therebetween. The delay is provided by a doublet register having a first register coupled to a second register, the two registers operative on one of the clock domains. Additionally, a clock selector is operative on two clocks which are each accompanied by a clock availability signal where the state machine provides a variety of states to create a dead zone between selections, and to bring the state machine to a known state until a clock signal is again available.