Clock Selector Circuit for Phase-Aligned Clock Switching
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Solution Overview
Problem
Switching between different clock signals in electronic circuits can result in frequency fluctuations and errors due to phase misalignment, particularly when switching from a high-accuracy crystal oscillator to a lower-power digitally controlled oscillator, leading to unpredictable output clock signals.
Innovation Solution
A clock selector circuit that detects phase alignment between reference and offset clock signals within a predetermined tolerance, switching only when the new clock signal is leading or trailing the current signal in phase, to minimize frequency fluctuations and maintain the output clock frequency close to the reference frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If switching is performed immediately upon receiving a switching signal without phase alignment detection, then switching speed is improved, but frequency fluctuations and switching artefacts increase
Solution Approach 1:
The switching circuitry performs phase alignment detection before executing the clock signal switch. This preliminary action ensures that the transition occurs only when the reference and offset clock signals are properly synchronized, preventing frequency fluctuations and switching artefacts while maintaining reliable output clock signal stability
2Reliability
If phase alignment detection with predetermined tolerance is implemented, then output clock frequency stability is improved, but switching response time increases
Solution Approach 1:
The switching circuitry uses a predetermined tolerance threshold for phase alignment detection that balances stability and response time. By adjusting this parameter, the circuit achieves sufficient phase synchronization to prevent frequency fluctuations while minimizing the time delay before switching can occur
3Measurement precision
If crystal oscillator is used for high accuracy clock signal, then clock accuracy is improved, but power consumption increases
Solution Approach 1:
The system dynamically switches between crystal oscillator and offset clock signal sources based on operational requirements. The switching circuitry selects the high-accuracy crystal oscillator when precision is critical and transitions to the lower-power offset signal when full accuracy is not required, optimizing the balance between clock accuracy and power consumption
4Use of energy by moving object
If offset clock signal is used for lower power consumption, then power efficiency is improved, but clock accuracy deteriorates
Solution Approach 1:
The switching circuitry acts as an intermediary that selectively connects the output to either the high-accuracy crystal oscillator or the low-power offset clock signal based on system needs. This mediator enables the system to achieve power efficiency when using the offset signal while maintaining the option to access high accuracy when required
Data Source
AI summary
A clock selector circuit includes a first input for receiving a reference clock signal having a reference frequency, a second input for receiving an offset clock signal having an offset frequency, a clock output for outputting the reference or offset clock signal, and switching circuitry. The switching circuitry includes a switching input and sign detector circuitry that outputs a sign signal indicating whether the reference clock signal is leading the offset clock signal in phase. In response to receiving a switching signal, the switching circuitry detects when like edges of the reference clock signal and the offset clock signal are aligned to within a predetermined tolerance, with the new signal leading the current signal if the offset frequency is lower than the reference frequency, or with the new clock signal trailing the current clock signal if not. In response, the switching circuitry switches to outputting the new clock signal.