Clock Selector Circuit for Zero-Crossing Clock Switching
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Solution Overview
Problem
Switching between clock signals derived from different oscillators, such as crystal and RC oscillators, can introduce switching artefacts that distort clock cycles, leading to frequency shifts outside specified limits and potential errors, especially in battery-powered IoT sensors and SoC devices.
Innovation Solution
A clock selector circuit that uses a phase difference detector to align the phases of two input clock signals by detecting a zero-crossing point, allowing seamless switching between them without requiring a higher-frequency third clock signal, using only the input clock signals themselves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If switching is performed directly between clock signals from different oscillators, then switching speed is improved, but switching artefacts distort clock cycles causing frequency shifts
Solution Approach 1:
The phase difference detector proactively monitors the phase relationship between clock signals before switching occurs. By detecting when the phase difference crosses zero in advance, the system prepares for switching at the optimal moment, preventing distortion artifacts that would otherwise corrupt the clock cycle during transition.
Solution Approach 2:
The phase difference detector acts as an intermediary between the two clock signals and the switching mechanism. It measures the phase relationship and provides timing information that mediates the switching operation, ensuring it occurs at the precise moment when phase alignment minimizes distortion.
2Measurement precision
If a higher-frequency third clock signal is used for switching, then switching precision is improved, but device complexity and power consumption increase
Solution Approach 1:
The system uses its existing clock signals to perform the switching function without requiring an external higher-frequency clock. The phase difference detector utilizes the two input clock signals themselves to generate the switching timing information, making the system self-sufficient and avoiding additional complexity from extra clock sources.
Solution Approach 2:
The existing clock signals serve dual purposes: they are both the signals being switched and the reference for determining when to switch. This multi-functionality eliminates the need for a separate higher-frequency switching clock, reducing overall system complexity while maintaining switching precision.
3Measurement precision
If a higher-frequency third clock signal is used for switching, then switching precision is improved, but power consumption increases
Solution Approach 1:
The system derives switching timing information from its existing clock signals rather than consuming additional power to run a separate higher-frequency clock source. This self-service approach maintains switching precision while minimizing power consumption by reusing available signals.
4Device complexity
If direct switching between misaligned clock signals is performed, then switching simplicity is improved, but output clock frequency shifts outside specified range
Solution Approach 1:
The phase difference detector performs preliminary monitoring of the phase relationship before switching occurs. By detecting the zero-crossing point in advance, the system ensures switching happens at the precise moment of phase alignment, maintaining output frequency accuracy within specified ranges while keeping the switching mechanism itself relatively simple.
Solution Approach 2:
The phase difference detector provides feedback about the phase relationship between clock signals to the switching mechanism. This feedback loop ensures switching occurs only when phase conditions are appropriate, maintaining frequency accuracy without requiring complex switching circuitry.
Data Source
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Figure 2
AI summary
A clock selector circuit (1) comprises a first input for receiving a first input clock signal (CLK1) having a first frequency, and a second input for receiving a second input clock signal (CLK2) having a second frequency, the second frequency differing from the first frequency by a frequency offset. The clock selector circuit (1) further comprises a clock output for outputting an output clock signal (CLK_OUT), a phase difference detector (7) and switching circuitry (5, 6). The phase difference detector (7) is configured to detect when a phase difference, over time, between the first input clock signal (CLK1) and the second input clock signal (CLK2), determined using a predetermined type of clock edge, being either a rising edge or a falling edge, crosses zero, and to signal this zero crossing to the switching circuitry (5, 6). The switching circuitry (5, 6) is configured, in response to receiving a zero-crossing signal from the phase difference detector (7), to detect an edge of opposite type to the predetermined type in the first input clock signal (CLK1) or in the second input clock signal (CLK2), and, in response to detecting said edge of opposite type, to switch the output clock signal (CLK_OUT) between the first input clock signal (CLK1) and the second input clock signal (CLK2).