Clock Shaper Circuit for 2 GHz Transition Fault Testing
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Solution Overview
Problem
Current clock shaper circuits in deep sub-micron CMOS technology struggle to provide clock pulses at high frequencies for at-speed transition fault testing, leading to increased logic depth and synchronization issues, which impede effective testing of integrated circuits operating at frequencies above 1.2 GHz.
Innovation Solution
A clock shaper circuit design that includes a synchronizing circuit, clock leaker circuit, and multiplexer, operating at functional clock frequencies of 1.5 GHz to 2 GHz, with logic depth not exceeding 2, to synchronize scan enable signals with clock pulses, ensuring timely generation of clock pulses during the launch and capture phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current clock shaper circuits are used in deep sub-micron CMOS technology, then clock pulses can be generated, but the logic depth increases and synchronization issues occur at frequencies above 1.2 GHz
Solution Approach 1:
The clock shaper circuit is divided into multiple independent modules: a scan enable signal synchronizing circuit that generates synchronized scan enable signals, and a clock leaker circuit that generates clock pulses based on these synchronized signals. This segmentation reduces the logic depth of each individual module, enabling operation at higher frequencies above 1.2 GHz while maintaining manageable complexity in each segment.
Solution Approach 2:
The scan enable signal synchronizing circuit performs preliminary synchronization of the scan enable signal before it is used by the clock leaker circuit. This preliminary action ensures that the clock pulse generation is properly synchronized with the scan operations, preventing synchronization issues and allowing the circuit to operate reliably at high frequencies without increasing overall logic depth.
2Productivity
If clock pulses are generated at high frequencies for at-speed transition fault testing, then testing speed improves, but synchronization issues and logic depth increase
Solution Approach 1:
The clock shaper circuit uses the synchronized scan enable signal as a feedback mechanism to control the generation of clock pulses. The scan enable signal synchronizing circuit continuously monitors and synchronizes the scan enable signal, and this synchronized signal directly controls the clock leaker circuit. This feedback-based control ensures that clock pulses are generated only when properly synchronized with scan operations, maintaining reliability even at high testing speeds above 1.2 GHz.
3Reliability
If logic depth is reduced to below 2, then synchronization is improved, but circuit design complexity increases
Solution Approach 1:
The circuit is segmented into two main functional blocks: the scan enable signal synchronizing circuit and the clock leaker circuit. Each block has a logic depth of less than 2, achieving the synchronization requirement. The segmentation distributes the design complexity across modular units, making the overall design manageable despite the stringent logic depth constraint.
Solution Approach 2:
The scan enable signal synchronizing circuit serves multiple functions: it synchronizes the scan enable signal, generates control signals for the clock leaker circuit, and ensures proper timing alignment for at-speed transition fault testing. This multi-functionality reduces the need for additional dedicated circuits, thereby managing design complexity while achieving the required logic depth of less than 2 for synchronization.
Data Source
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AI summary
An integrated circuit for transition fault testing comprises a synchronizing circuit including a first set of shift registers coupled to receive a scan enable signal and to provide a synchronizing signal based on the scan enable signal; a clock leaker circuit coupled to the synchronizing circuit and including a second set of shift registers coupled to receive a first clock signal based on the synchronizing signal and to provide a second clock signal that includes a set of pulses; and a multiplexer (MUX) that includes a first input coupled to receive a shift clock, a second input coupled to the clock leaker circuit to receive the second clock signal, and an output configured to provide an output clock signal that includes a second set of pulses.