Programmable Clock Shaping with Independent Edge Skew Control
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Solution Overview
Problem
Existing clock trimmer circuits in computing systems are limited by their inability to independently program the rising and falling edges of a clock signal, leading to a fixed duty cycle and reduced performance due to lock-step delay, which can slow down clock frequency under certain conditions.
Innovation Solution
A programmable clock shaping circuit that includes rising edge and falling edge skew logic, allowing for independent adjustment of the rising and falling edges of a clock signal, enabling real-time re-programming without stopping the clock source, thereby dynamically shaping the clock signal to optimize computing system speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If lock-step delay is applied to both rising and falling edges, then duty cycle is fixed, but performance speed is reduced
Solution Approach 1:
The clock trimmer circuit is segmented into separate rising edge delay logic and falling edge delay logic, allowing independent programming of each edge. This segmentation enables the circuit to avoid lock-step delay constraints and optimize performance speed by adjusting only the necessary edge delays based on actual processing operation times.
Solution Approach 2:
The circuit implements dynamic delay adjustment by allowing the rising edge delay and falling edge delay to be independently programmed based on real-time processing operation times. This dynamic capability enables the duty cycle to be adjusted flexibly rather than fixed, thereby improving performance speed without compromising timing stability.
2Speed
If independent programming of rising and falling edges is implemented, then performance speed is improved, but device complexity increases
Solution Approach 1:
The clock trimmer circuit is divided into separate rising edge delay logic and falling edge delay logic modules. Each module independently controls its respective edge delay, which simplifies the overall design and programming compared to a monolithic approach. This segmentation allows for modular implementation that manages complexity while enabling independent edge programming for improved performance.
3Stability of the object's composition
If clock frequency is slowed by lock-step delay, then duty cycle is maintained, but productivity decreases
Solution Approach 1:
The circuit enables dynamic adjustment of rising and falling edge delays independently, allowing the duty cycle to be optimized for different processing operation times. This dynamic capability eliminates the need to slow down clock frequency to maintain duty cycle, thereby improving productivity and computing system performance while maintaining timing stability.
Data Source
AI summary
In one embodiment, a microprocessor includes one or more processing cores. At least one processing core includes a clock shaping circuit that is configured to receive a clock input signal. The clock shaping circuit includes rising edge skew logic that is configured to selectively delay a rising edge of the clock input signal and falling edge skew logic that is configured to selectively delay a falling edge of the clock input signal independent of adjustment of the rising edge.