Clock Network Shielding and Phase Skew for Power Spike Reduction
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Solution Overview
Problem
Existing clock networks in VLSI devices experience power supply collapses due to transient currents, leading to logic delays and functional faults, with prior solutions requiring excessive decoupling capacitance that increases cost and area, and failing to distinguish between on-chip and off-chip currents.
Innovation Solution
The solution involves adjusting current spikes by smearing or shifting them across the clock cycle through techniques like uniform current smearing, mixing active high and low clock signals, and configuring shield wires to distribute current spikes, thereby reducing voltage sags by balancing capacitive loads and adjusting clock polarities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitance is added to address power supply collapse, then power supply stability is improved, but device area and cost increase significantly
Solution Approach 1:
The patent changes the temporal distribution parameter of clock current by introducing skew between clock signals. Instead of adding capacitance to store energy, the solution redistributes current demand over time by delaying clock edges in different regions, thereby smoothing the overall current profile without requiring additional decoupling capacitance area
Solution Approach 2:
The clock network is segmented into multiple regions with different clock phases. By dividing the monolithic clock signal into distributed phased signals, the patent reduces the simultaneous switching activity in any single region, thereby reducing peak current demands without adding decoupling capacitance
2Reliability
If decoupling capacitance is added to reduce voltage sags, then power supply stability is improved, but manufacturing cost increases
Solution Approach 1:
The patent modifies the temporal parameter of clock current delivery by introducing phase skew. This changes when current is drawn in different parts of the device, smoothing the aggregate current profile and reducing voltage sags without requiring expensive additional decoupling capacitance components
3Device complexity
If traditional clock networks are used, then device complexity is low, but power spikes cause logic delays and functional faults
Solution Approach 1:
The patent introduces dynamic phase adjustment to the clock network. By making the clock phase relationships adjustable and region-specific rather than static and uniform, the system can dynamically adapt to local current demands and reduce power spikes that cause functional failures
Solution Approach 2:
Different regions of the device receive clock signals with locally optimized phases. This local quality approach allows each region to operate with clock timing that minimizes its contribution to overall power spikes, improving device functionality without uniformly increasing complexity across the entire system
4Reliability
If all clock current is considered important, then power supply stability is addressed, but the solution neglects the difference between on-chip and off-chip currents
Solution Approach 1:
The patent applies different clock phase strategies to different regions based on their specific current characteristics. By recognizing that different parts of the chip have different current profiles and power distribution characteristics, the solution optimizes clock timing locally rather than applying a uniform approach, reducing overall power spikes without excessive complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power spikes and voltage transients, improving the reliability of VLSI devices by evenly distributing current across the clock cycle and minimizing noise in the power supply network.
Implementation Method 1
The analysis in FIGS. 1a-b and 2a-d show the details of how a logic transition to a voltage that is the same as the opposite terminal in the parasitic capacitcance causes current that flows completely within the integrated circuit
Data Source
AI summary
A clock network includes a first plurality of shield wires associated with a first plurality of clock lines and a second plurality of shield wires associated with a second plurality of clock lines. The clock network also includes a first plurality of clock activity program circuits associated with the first plurality of clock lines and a second plurality of clock activity program circuits associated with the second plurality of clock lines, wherein the first and second plurality of shield wires and the first and second plurality clock activity program circuits are configured to reduce power spikes.