Clock Signal Shielding Layout for Multiphase Timing Accuracy
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Solution Overview
Problem
Semiconductor memories face issues with timing deviations in clock signals, which can lead to erroneous operations, especially at higher frequencies, due to varying voltage conditions, affecting the proper functioning of internal circuits.
Innovation Solution
The implementation of a clock dividing circuit that generates multiphase clock signals with controlled phase and frequency, along with shielding conductive lines to maintain consistent voltage conditions for the clock signals, mitigates timing deviations and ensures accurate operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signal frequency is increased to improve memory operation speed, then productivity is improved, but timing deviations increase causing erroneous operations
Solution Approach 1:
The patent segments the single clock signal into multiple phase-shifted clock signals (e.g., four phases at 90-degree intervals) using a clock dividing circuit. This segmentation allows parallel operation of memory circuits with different phase clocks, achieving higher effective throughput while maintaining timing accuracy through controlled phase relationships rather than relying on single high-frequency clock edges.
Solution Approach 2:
The patent introduces conductive lines as intermediary shielding structures between clock signal lines. These intermediary conductive lines act as electromagnetic shields that mediate the electrical environment, reducing crosstalk and voltage fluctuations between adjacent clock lines, thereby maintaining timing accuracy at higher frequencies.
2Adaptability or versatility
If voltage conditions vary in internal circuits, then adaptability is improved for different operating conditions, but timing deviations occur causing operational errors
Solution Approach 1:
The patent applies equipotentiality by providing consistent voltage conditions to multiple conductive lines through dedicated voltage supply circuits. This ensures that clock signals propagating through different internal circuits experience uniform voltage environments, eliminating timing deviations caused by voltage variations while maintaining the ability to adapt to different operating conditions through controlled voltage levels.
3Measurement precision
If conductive lines are added for voltage control, then timing accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the conductive lines: they serve both as electrical interconnects for clock signals and as shielded structures for voltage control. By combining signal transmission and electromagnetic shielding functions into the same conductive infrastructure, the patent achieves timing accuracy improvements without proportionally increasing device complexity.
Data Source
AI summary
Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.