Clock Shifter Circuit Without Gate Boosting for Lower Delay
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Solution Overview
Problem
Conventional clock shifter circuits require high-current supply voltages to boost transistor gate voltages, leading to larger transistor switches and capacitors, increased power consumption, and higher silicon area, as well as propagation delays in the output clock signal.
Innovation Solution
A clock shifter circuit design that eliminates the need for boosting transistor gate voltages by using cross-coupled transistor switches and capacitors with long charging time constants, allowing for minimum-sized switches and reduced power consumption, and removes the series-coupled output switch to minimize propagation delay and silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-current supply voltage is used to boost transistor gate voltages, then transistor switches can be activated, but power consumption increases and silicon area increases
Solution Approach 1:
The patent removes the high-current supply voltage boosting circuitry from the clock shifter design. By eliminating the need for voltage boosting, the circuit avoids the associated power consumption and silicon area requirements while maintaining reliable transistor activation through alternative circuit toplogy using cross-coupled switches and capacitors
Solution Approach 2:
The patent introduces coupling capacitors as intermediary elements that transfer clock signals between voltage domains without requiring high-current supply voltages. These capacitors mediate the voltage level transition by charging and discharging to transfer the clock signal from the first voltage domain to the second voltage domain
2Reliability
If high-current supply voltage is used to boost transistor gate voltages, then transistor switches can be activated, but transistor switches and capacitors must be larger
Solution Approach 1:
The patent removes the voltage boosting circuitry that required large transistor switches and capacitors. By eliminating the need to boost gate voltages above the supply voltage, the circuit can use minimum-sized transistors and smaller capacitors, reducing overall silicon area while maintaining proper transistor activation
Solution Approach 2:
The patent changes the operating parameters of the transistor switches by designing them to operate without gate voltage boosting. The transistors are sized and biased to function correctly with gate voltages within the normal supply voltage range, allowing for smaller device dimensions and reduced silicon area
3Reliability
If series-coupled output switch is used to boost output node voltage level, then transistor switches can be activated, but propagation delay increases
Solution Approach 1:
The patent removes the series-coupled output switch from the circuit topology. By eliminating this switching element, the propagation delay associated with its operation is removed, while transistor activation is maintained through the cross-coupled switch configuration and capacitor-based voltage transfer mechanism
4Reliability
If series-coupled output switch is used to boost output node voltage level, then transistor switches can be activated, but silicon area increases
Solution Approach 1:
The patent removes the series-coupled output switch and its associated control circuitry. This elimination reduces the silicon area required for the clock shifter while maintaining proper transistor activation through the alternative cross-coupled switch and capacitor topology
Data Source
AI summary
A clock shifter circuit may receive a input clock in a first voltage domain and may generate a level-shifted output clock in a second voltage domain. The circuit may include a cross-coupled pair of transistor switches and a pair of capacitors. Each switch may have a drain coupled to one of the capacitors, a source coupled to a circuit supply voltage, and a gate coupled to the other capacitor. One capacitor may receive a true input clock version, while the other may receive a complement version. Each capacitor, in an alternating manner, may activate an opposing transistor switch to charge its capacitor during an active phase of its respective input clock. The circuit may generate the output clock from an output node connected between one of the transistor switches and its capacitor. The output clock may drive a load directly coupled to the output node.